Predictive technology model for nano-CMOS design exploration

Yu Cao; Wei Zhao

doi:10.1109/NANONET.2006.346227

Predictive technology model for nano-CMOS design exploration

Yu Cao, Wei Zhao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

19 Scopus citations

Abstract

Predictive MOSFET model is critical for early circuit design research. In this work, a new generation of Predictive Technology Model (PTM) is developed, covering emerging physical effects and alternative structures. Based on physical models and early stage silicon data, PTM of bulk and double-gate devices are successfully generated from 130nm to 32nm technology nodes, with effective channel length down to 13nm. By tuning only ten primary parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of the current is below 10% for both NMOS and PMOS. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. PTM is available on line at http://www.eas.asu.edu/~ptm.

Original language	English (US)
Title of host publication	2006 1st International Conference on Nano-Networks and Workshops, Nano-Net
DOIs	https://doi.org/10.1109/NANONET.2006.346227
State	Published - 2006
Event	2006 1st International Conference on Nano-Networks and Workshops, Nano-Net - Lausanne, Switzerland Duration: Sep 14 2006 → Sep 16 2006

Publication series

Name	2006 1st International Conference on Nano-Networks and Workshops, Nano-Net

Other

Other	2006 1st International Conference on Nano-Networks and Workshops, Nano-Net
Country/Territory	Switzerland
City	Lausanne
Period	9/14/06 → 9/16/06

Keywords

Early design exploration
FinFET
Predictive modeling
Process variations
Technology scaling

ASJC Scopus subject areas

Computational Theory and Mathematics
Computer Networks and Communications

Access to Document

10.1109/NANONET.2006.346227

Cite this

Cao, Y & Zhao, W 2006, Predictive technology model for nano-CMOS design exploration. in 2006 1st International Conference on Nano-Networks and Workshops, Nano-Net., 4152810, 2006 1st International Conference on Nano-Networks and Workshops, Nano-Net, 2006 1st International Conference on Nano-Networks and Workshops, Nano-Net, Lausanne, Switzerland, 9/14/06. https://doi.org/10.1109/NANONET.2006.346227

@inproceedings{7cf9a0b079404609a76c633fb935db15,

title = "Predictive technology model for nano-CMOS design exploration",

abstract = "Predictive MOSFET model is critical for early circuit design research. In this work, a new generation of Predictive Technology Model (PTM) is developed, covering emerging physical effects and alternative structures. Based on physical models and early stage silicon data, PTM of bulk and double-gate devices are successfully generated from 130nm to 32nm technology nodes, with effective channel length down to 13nm. By tuning only ten primary parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of the current is below 10% for both NMOS and PMOS. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. PTM is available on line at http://www.eas.asu.edu/~ptm.",

keywords = "Early design exploration, FinFET, Predictive modeling, Process variations, Technology scaling",

author = "Yu Cao and Wei Zhao",

year = "2006",

doi = "10.1109/NANONET.2006.346227",

language = "English (US)",

isbn = "142440391X",

series = "2006 1st International Conference on Nano-Networks and Workshops, Nano-Net",

booktitle = "2006 1st International Conference on Nano-Networks and Workshops, Nano-Net",

note = "2006 1st International Conference on Nano-Networks and Workshops, Nano-Net ; Conference date: 14-09-2006 Through 16-09-2006",

}

TY - GEN

T1 - Predictive technology model for nano-CMOS design exploration

AU - Cao, Yu

AU - Zhao, Wei

PY - 2006

Y1 - 2006

N2 - Predictive MOSFET model is critical for early circuit design research. In this work, a new generation of Predictive Technology Model (PTM) is developed, covering emerging physical effects and alternative structures. Based on physical models and early stage silicon data, PTM of bulk and double-gate devices are successfully generated from 130nm to 32nm technology nodes, with effective channel length down to 13nm. By tuning only ten primary parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of the current is below 10% for both NMOS and PMOS. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. PTM is available on line at http://www.eas.asu.edu/~ptm.

AB - Predictive MOSFET model is critical for early circuit design research. In this work, a new generation of Predictive Technology Model (PTM) is developed, covering emerging physical effects and alternative structures. Based on physical models and early stage silicon data, PTM of bulk and double-gate devices are successfully generated from 130nm to 32nm technology nodes, with effective channel length down to 13nm. By tuning only ten primary parameters, PTM can be easily customized to cover a wide range of process uncertainties. The accuracy of PTM predictions is comprehensively verified with published silicon data: the error of the current is below 10% for both NMOS and PMOS. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime. PTM is available on line at http://www.eas.asu.edu/~ptm.

KW - Early design exploration

KW - FinFET

KW - Predictive modeling

KW - Process variations

KW - Technology scaling

UR - http://www.scopus.com/inward/record.url?scp=50149084763&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=50149084763&partnerID=8YFLogxK

U2 - 10.1109/NANONET.2006.346227

DO - 10.1109/NANONET.2006.346227

M3 - Conference contribution

AN - SCOPUS:50149084763

SN - 142440391X

SN - 9781424403912

T3 - 2006 1st International Conference on Nano-Networks and Workshops, Nano-Net

BT - 2006 1st International Conference on Nano-Networks and Workshops, Nano-Net

T2 - 2006 1st International Conference on Nano-Networks and Workshops, Nano-Net

Y2 - 14 September 2006 through 16 September 2006

ER -

Predictive technology model for nano-CMOS design exploration

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

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