TY - GEN
T1 - Precision timed infrastructure
T2 - 2013 3rd Electronic System Level Synthesis Conference, ESLsyn 2013
AU - Broman, David
AU - Zimmer, Michael
AU - Kim, Yooseong
AU - Kim, Hokeun
AU - Cai, Jian
AU - Shrivastava, Aviral
AU - Edwards, Stephen A.
AU - Lee, Edward A.
PY - 2013/9/9
Y1 - 2013/9/9
N2 - In general-purpose software applications, computation time is just a quality factor: faster is better. In cyber-physical systems (CPS), however, computation time is a correctness factor: missed deadlines for hard real-time applications, such as avionics and automobiles, can result in devastating, life-threatening conse-quences. Although many modern modeling languages for CPS include the notion of time, implementation languages such as Clack any temporal semantics. Consequently, models and programs for CPS are neither portable nor guaranteed to execute correctly on the real system; timing is merely a side effect of the realization of a software system on a specific hardware platform. In this position paper, we present the research initiative for a precision timed (PRET) infrastructure, consisting of languages, compilers, and microarchitectures, where timing is a correctness factor. In particular, the timing semantics in models and programs must be preserved during compilation to ensure that the behavior of real systems complies with models. We also outline new research and design challenges present in such an infrastructure.
AB - In general-purpose software applications, computation time is just a quality factor: faster is better. In cyber-physical systems (CPS), however, computation time is a correctness factor: missed deadlines for hard real-time applications, such as avionics and automobiles, can result in devastating, life-threatening conse-quences. Although many modern modeling languages for CPS include the notion of time, implementation languages such as Clack any temporal semantics. Consequently, models and programs for CPS are neither portable nor guaranteed to execute correctly on the real system; timing is merely a side effect of the realization of a software system on a specific hardware platform. In this position paper, we present the research initiative for a precision timed (PRET) infrastructure, consisting of languages, compilers, and microarchitectures, where timing is a correctness factor. In particular, the timing semantics in models and programs must be preserved during compilation to ensure that the behavior of real systems complies with models. We also outline new research and design challenges present in such an infrastructure.
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M3 - Conference contribution
AN - SCOPUS:84883368332
SN - 9782953998771
T3 - Proceedings of the electronic system level synthesis conference
BT - Proceedings of the 2013 Electronic System Level Synthesis Conference, ESLsyn 2013
Y2 - 31 May 2013 through 1 June 2013
ER -