Precision timed infrastructure: Design challenges

David Broman, Michael Zimmer, Yooseong Kim, Hokeun Kim, Jian Cai, Aviral Shrivastava, Stephen A. Edwards, Edward A. Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

In general-purpose software applications, computation time is just a quality factor: faster is better. In cyber-physical systems (CPS), however, computation time is a correctness factor: missed deadlines for hard real-time applications, such as avionics and automobiles, can result in devastating, life-threatening conse-quences. Although many modern modeling languages for CPS include the notion of time, implementation languages such as Clack any temporal semantics. Consequently, models and programs for CPS are neither portable nor guaranteed to execute correctly on the real system; timing is merely a side effect of the realization of a software system on a specific hardware platform. In this position paper, we present the research initiative for a precision timed (PRET) infrastructure, consisting of languages, compilers, and microarchitectures, where timing is a correctness factor. In particular, the timing semantics in models and programs must be preserved during compilation to ensure that the behavior of real systems complies with models. We also outline new research and design challenges present in such an infrastructure.

Original languageEnglish (US)
Title of host publicationProceedings of the 2013 Electronic System Level Synthesis Conference, ESLsyn 2013
StatePublished - Sep 9 2013
Event2013 3rd Electronic System Level Synthesis Conference, ESLsyn 2013 - Austin, TX, United States
Duration: May 31 2013Jun 1 2013

Publication series

NameProceedings of the electronic system level synthesis conference
ISSN (Print)2117-4628

Other

Other2013 3rd Electronic System Level Synthesis Conference, ESLsyn 2013
CountryUnited States
CityAustin, TX
Period5/31/136/1/13

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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  • Cite this

    Broman, D., Zimmer, M., Kim, Y., Kim, H., Cai, J., Shrivastava, A., Edwards, S. A., & Lee, E. A. (2013). Precision timed infrastructure: Design challenges. In Proceedings of the 2013 Electronic System Level Synthesis Conference, ESLsyn 2013 [6573221] (Proceedings of the electronic system level synthesis conference).