PPL integrated circuit design methodology

Brent E. Nelson, Darryl R. Morrell, Christopher J. Read, Kent F. Smith

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

Path programmable logic (PPL) is an integrated circuit design methodology offering small layout areas, greatly reduced design time, and a high degree of technology independence. In this paper, the structure of PPL is presented, and the details of one implementation, static CMOS PPL, are shown. A conceptual model of PPL design using truth and state tables is given. A database format is presented, and the design system using this database is described. Benchmarks comparing PPL to other design methodologies show PPL compares favourably with custom design in terms of layout area while providing significant savings in design time.

Original languageEnglish (US)
Pages (from-to)481-488
Number of pages8
JournalComputer-Aided Design
Volume18
Issue number9
DOIs
StatePublished - Nov 1986
Externally publishedYes

Keywords

  • integrated circuit design
  • integrated circuit technology
  • path programmable logic

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Industrial and Manufacturing Engineering

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