PPL integrated circuit design methodology

Brent E. Nelson; Darryl R. Morrell; Christopher J. Read; Kent F. Smith

doi:10.1016/0010-4485(86)90005-9

PPL integrated circuit design methodology

Brent E. Nelson, Darryl R. Morrell, Christopher J. Read, Kent F. Smith

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

Path programmable logic (PPL) is an integrated circuit design methodology offering small layout areas, greatly reduced design time, and a high degree of technology independence. In this paper, the structure of PPL is presented, and the details of one implementation, static CMOS PPL, are shown. A conceptual model of PPL design using truth and state tables is given. A database format is presented, and the design system using this database is described. Benchmarks comparing PPL to other design methodologies show PPL compares favourably with custom design in terms of layout area while providing significant savings in design time.

Original language	English (US)
Pages (from-to)	481-488
Number of pages	8
Journal	Computer-Aided Design
Volume	18
Issue number	9
DOIs	https://doi.org/10.1016/0010-4485(86)90005-9
State	Published - Nov 1986
Externally published	Yes

Keywords

integrated circuit design
integrated circuit technology
path programmable logic

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Industrial and Manufacturing Engineering

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10.1016/0010-4485(86)90005-9

Cite this

@article{f52bd0a44ee64db19980f08f3a6e0d46,

title = "PPL integrated circuit design methodology",

abstract = "Path programmable logic (PPL) is an integrated circuit design methodology offering small layout areas, greatly reduced design time, and a high degree of technology independence. In this paper, the structure of PPL is presented, and the details of one implementation, static CMOS PPL, are shown. A conceptual model of PPL design using truth and state tables is given. A database format is presented, and the design system using this database is described. Benchmarks comparing PPL to other design methodologies show PPL compares favourably with custom design in terms of layout area while providing significant savings in design time.",

keywords = "integrated circuit design, integrated circuit technology, path programmable logic",

author = "Nelson, {Brent E.} and Morrell, {Darryl R.} and Read, {Christopher J.} and Smith, {Kent F.}",

year = "1986",

month = nov,

doi = "10.1016/0010-4485(86)90005-9",

language = "English (US)",

volume = "18",

pages = "481--488",

journal = "Computer-Aided Design",

issn = "0010-4485",

publisher = "Elsevier Limited",

number = "9",

}

TY - JOUR

T1 - PPL integrated circuit design methodology

AU - Nelson, Brent E.

AU - Morrell, Darryl R.

AU - Read, Christopher J.

AU - Smith, Kent F.

PY - 1986/11

Y1 - 1986/11

N2 - Path programmable logic (PPL) is an integrated circuit design methodology offering small layout areas, greatly reduced design time, and a high degree of technology independence. In this paper, the structure of PPL is presented, and the details of one implementation, static CMOS PPL, are shown. A conceptual model of PPL design using truth and state tables is given. A database format is presented, and the design system using this database is described. Benchmarks comparing PPL to other design methodologies show PPL compares favourably with custom design in terms of layout area while providing significant savings in design time.

AB - Path programmable logic (PPL) is an integrated circuit design methodology offering small layout areas, greatly reduced design time, and a high degree of technology independence. In this paper, the structure of PPL is presented, and the details of one implementation, static CMOS PPL, are shown. A conceptual model of PPL design using truth and state tables is given. A database format is presented, and the design system using this database is described. Benchmarks comparing PPL to other design methodologies show PPL compares favourably with custom design in terms of layout area while providing significant savings in design time.

KW - integrated circuit design

KW - integrated circuit technology

KW - path programmable logic

UR - http://www.scopus.com/inward/record.url?scp=0022811339&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022811339&partnerID=8YFLogxK

U2 - 10.1016/0010-4485(86)90005-9

DO - 10.1016/0010-4485(86)90005-9

M3 - Article

AN - SCOPUS:0022811339

SN - 0010-4485

VL - 18

SP - 481

EP - 488

JO - Computer-Aided Design

JF - Computer-Aided Design

IS - 9

ER -

PPL integrated circuit design methodology

Abstract

Keywords

ASJC Scopus subject areas

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