TY - GEN
T1 - Power efficient voltage islanding for systems-on-chip from a floorplanning perspective
AU - Ghosh, Pavel
AU - Sen, Arunabha
PY - 2010
Y1 - 2010
N2 - Power consumption can be significantly reduced in Systems-on-Chip (SoC) by scaling down the voltage levels of the Processing Elements (PEs). The power efficiency of this Voltage Islanding technique comes at the cost of energy and area overhead due to the level shifters between voltage islands. Moreover, from the physical design perspective it is not desirable to have an excessive number of voltage islands on the chip. Considering voltage islanding at an early phase of design as during floorplanning of the PEs can address various of these issues. In this paper, we propose a new cost function for the floorplanning objective different from the traditional floorplanning objective. The new cost function not only includes the overall area requirement, but also incorporates the overall power consumption and the design constraint imposed on the maximum number of voltage islands. We propose a greedy heuristic based on the proposed cost function for the floorplanning of the PEs with several voltage islands. Experimental results using benchmark data study the effect of several parameters on the outcome of the heuristic. It is evident from the results that power consumption can be significantly reduced using our algorithm without significant area overhead. The area obtained from the heuristic is also compared with the optimal, and found to be within 4% of the optimal on average, when area minimization is given the priority.
AB - Power consumption can be significantly reduced in Systems-on-Chip (SoC) by scaling down the voltage levels of the Processing Elements (PEs). The power efficiency of this Voltage Islanding technique comes at the cost of energy and area overhead due to the level shifters between voltage islands. Moreover, from the physical design perspective it is not desirable to have an excessive number of voltage islands on the chip. Considering voltage islanding at an early phase of design as during floorplanning of the PEs can address various of these issues. In this paper, we propose a new cost function for the floorplanning objective different from the traditional floorplanning objective. The new cost function not only includes the overall area requirement, but also incorporates the overall power consumption and the design constraint imposed on the maximum number of voltage islands. We propose a greedy heuristic based on the proposed cost function for the floorplanning of the PEs with several voltage islands. Experimental results using benchmark data study the effect of several parameters on the outcome of the heuristic. It is evident from the results that power consumption can be significantly reduced using our algorithm without significant area overhead. The area obtained from the heuristic is also compared with the optimal, and found to be within 4% of the optimal on average, when area minimization is given the priority.
UR - http://www.scopus.com/inward/record.url?scp=77953119440&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77953119440&partnerID=8YFLogxK
U2 - 10.1109/date.2010.5457124
DO - 10.1109/date.2010.5457124
M3 - Conference contribution
AN - SCOPUS:77953119440
SN - 9783981080162
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 654
EP - 657
BT - DATE 10 - Design, Automation and Test in Europe
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Design, Automation and Test in Europe Conference and Exhibition, DATE 2010
Y2 - 8 March 2010 through 12 March 2010
ER -