Power efficient voltage islanding for systems-on-chip from a floorplanning perspective

Pavel Ghosh, Arunabha Sen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Power consumption can be significantly reduced in Systems-on-Chip (SoC) by scaling down the voltage levels of the Processing Elements (PEs). The power efficiency of this Voltage Islanding technique comes at the cost of energy and area overhead due to the level shifters between voltage islands. Moreover, from the physical design perspective it is not desirable to have an excessive number of voltage islands on the chip. Considering voltage islanding at an early phase of design as during floorplanning of the PEs can address various of these issues. In this paper, we propose a new cost function for the floorplanning objective different from the traditional floorplanning objective. The new cost function not only includes the overall area requirement, but also incorporates the overall power consumption and the design constraint imposed on the maximum number of voltage islands. We propose a greedy heuristic based on the proposed cost function for the floorplanning of the PEs with several voltage islands. Experimental results using benchmark data study the effect of several parameters on the outcome of the heuristic. It is evident from the results that power consumption can be significantly reduced using our algorithm without significant area overhead. The area obtained from the heuristic is also compared with the optimal, and found to be within 4% of the optimal on average, when area minimization is given the priority.

Original languageEnglish (US)
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
Pages654-657
Number of pages4
StatePublished - 2010
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany
Duration: Mar 8 2010Mar 12 2010

Other

OtherDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010
CountryGermany
CityDresden
Period3/8/103/12/10

Fingerprint

Electric potential
Cost functions
Electric power utilization
Processing
System-on-chip

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Ghosh, P., & Sen, A. (2010). Power efficient voltage islanding for systems-on-chip from a floorplanning perspective. In Proceedings -Design, Automation and Test in Europe, DATE (pp. 654-657). [5457124]

Power efficient voltage islanding for systems-on-chip from a floorplanning perspective. / Ghosh, Pavel; Sen, Arunabha.

Proceedings -Design, Automation and Test in Europe, DATE. 2010. p. 654-657 5457124.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ghosh, P & Sen, A 2010, Power efficient voltage islanding for systems-on-chip from a floorplanning perspective. in Proceedings -Design, Automation and Test in Europe, DATE., 5457124, pp. 654-657, Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, Dresden, Germany, 3/8/10.
Ghosh P, Sen A. Power efficient voltage islanding for systems-on-chip from a floorplanning perspective. In Proceedings -Design, Automation and Test in Europe, DATE. 2010. p. 654-657. 5457124
Ghosh, Pavel ; Sen, Arunabha. / Power efficient voltage islanding for systems-on-chip from a floorplanning perspective. Proceedings -Design, Automation and Test in Europe, DATE. 2010. pp. 654-657
@inproceedings{484bd0757d5a43d4937616dc97cb5aa4,
title = "Power efficient voltage islanding for systems-on-chip from a floorplanning perspective",
abstract = "Power consumption can be significantly reduced in Systems-on-Chip (SoC) by scaling down the voltage levels of the Processing Elements (PEs). The power efficiency of this Voltage Islanding technique comes at the cost of energy and area overhead due to the level shifters between voltage islands. Moreover, from the physical design perspective it is not desirable to have an excessive number of voltage islands on the chip. Considering voltage islanding at an early phase of design as during floorplanning of the PEs can address various of these issues. In this paper, we propose a new cost function for the floorplanning objective different from the traditional floorplanning objective. The new cost function not only includes the overall area requirement, but also incorporates the overall power consumption and the design constraint imposed on the maximum number of voltage islands. We propose a greedy heuristic based on the proposed cost function for the floorplanning of the PEs with several voltage islands. Experimental results using benchmark data study the effect of several parameters on the outcome of the heuristic. It is evident from the results that power consumption can be significantly reduced using our algorithm without significant area overhead. The area obtained from the heuristic is also compared with the optimal, and found to be within 4{\%} of the optimal on average, when area minimization is given the priority.",
author = "Pavel Ghosh and Arunabha Sen",
year = "2010",
language = "English (US)",
isbn = "9783981080162",
pages = "654--657",
booktitle = "Proceedings -Design, Automation and Test in Europe, DATE",

}

TY - GEN

T1 - Power efficient voltage islanding for systems-on-chip from a floorplanning perspective

AU - Ghosh, Pavel

AU - Sen, Arunabha

PY - 2010

Y1 - 2010

N2 - Power consumption can be significantly reduced in Systems-on-Chip (SoC) by scaling down the voltage levels of the Processing Elements (PEs). The power efficiency of this Voltage Islanding technique comes at the cost of energy and area overhead due to the level shifters between voltage islands. Moreover, from the physical design perspective it is not desirable to have an excessive number of voltage islands on the chip. Considering voltage islanding at an early phase of design as during floorplanning of the PEs can address various of these issues. In this paper, we propose a new cost function for the floorplanning objective different from the traditional floorplanning objective. The new cost function not only includes the overall area requirement, but also incorporates the overall power consumption and the design constraint imposed on the maximum number of voltage islands. We propose a greedy heuristic based on the proposed cost function for the floorplanning of the PEs with several voltage islands. Experimental results using benchmark data study the effect of several parameters on the outcome of the heuristic. It is evident from the results that power consumption can be significantly reduced using our algorithm without significant area overhead. The area obtained from the heuristic is also compared with the optimal, and found to be within 4% of the optimal on average, when area minimization is given the priority.

AB - Power consumption can be significantly reduced in Systems-on-Chip (SoC) by scaling down the voltage levels of the Processing Elements (PEs). The power efficiency of this Voltage Islanding technique comes at the cost of energy and area overhead due to the level shifters between voltage islands. Moreover, from the physical design perspective it is not desirable to have an excessive number of voltage islands on the chip. Considering voltage islanding at an early phase of design as during floorplanning of the PEs can address various of these issues. In this paper, we propose a new cost function for the floorplanning objective different from the traditional floorplanning objective. The new cost function not only includes the overall area requirement, but also incorporates the overall power consumption and the design constraint imposed on the maximum number of voltage islands. We propose a greedy heuristic based on the proposed cost function for the floorplanning of the PEs with several voltage islands. Experimental results using benchmark data study the effect of several parameters on the outcome of the heuristic. It is evident from the results that power consumption can be significantly reduced using our algorithm without significant area overhead. The area obtained from the heuristic is also compared with the optimal, and found to be within 4% of the optimal on average, when area minimization is given the priority.

UR - http://www.scopus.com/inward/record.url?scp=77953119440&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77953119440&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:77953119440

SN - 9783981080162

SP - 654

EP - 657

BT - Proceedings -Design, Automation and Test in Europe, DATE

ER -