Power efficient voltage islanding for systems-on-chip from a floorplanning perspective

Pavel Ghosh, Arunabha Sen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Power consumption can be significantly reduced in Systems-on-Chip (SoC) by scaling down the voltage levels of the Processing Elements (PEs). The power efficiency of this Voltage Islanding technique comes at the cost of energy and area overhead due to the level shifters between voltage islands. Moreover, from the physical design perspective it is not desirable to have an excessive number of voltage islands on the chip. Considering voltage islanding at an early phase of design as during floorplanning of the PEs can address various of these issues. In this paper, we propose a new cost function for the floorplanning objective different from the traditional floorplanning objective. The new cost function not only includes the overall area requirement, but also incorporates the overall power consumption and the design constraint imposed on the maximum number of voltage islands. We propose a greedy heuristic based on the proposed cost function for the floorplanning of the PEs with several voltage islands. Experimental results using benchmark data study the effect of several parameters on the outcome of the heuristic. It is evident from the results that power consumption can be significantly reduced using our algorithm without significant area overhead. The area obtained from the heuristic is also compared with the optimal, and found to be within 4% of the optimal on average, when area minimization is given the priority.

Original languageEnglish (US)
Title of host publicationDATE 10 - Design, Automation and Test in Europe
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages654-657
Number of pages4
ISBN (Print)9783981080162
DOIs
StatePublished - 2010
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany
Duration: Mar 8 2010Mar 12 2010

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

OtherDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010
CountryGermany
CityDresden
Period3/8/103/12/10

ASJC Scopus subject areas

  • Engineering(all)

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    Ghosh, P., & Sen, A. (2010). Power efficient voltage islanding for systems-on-chip from a floorplanning perspective. In DATE 10 - Design, Automation and Test in Europe (pp. 654-657). [5457124] (Proceedings -Design, Automation and Test in Europe, DATE). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/date.2010.5457124