Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design

Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

This paper investigates pipelining methodologies for the ultra low voltage regime. Based on an analytical model and simulations, we propose a pipelining technique that provides higher energy efficiency and performance than conventional approaches to ultra low voltage design. Two-phase latch based design and sequential circuit optimizations are also proposed to further improve energy efficiency and performance. Silicon results demonstrate a 16b multiplier using the approaches in 65nm CMOS improve energy efficiency by 30% and performance by 60%.

Original languageEnglish (US)
Title of host publicationProceedings - Design Automation Conference
Pages990-995
Number of pages6
StatePublished - 2011
Event2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 - San Diego, CA, United States
Duration: Jun 5 2011Jun 9 2011

Other

Other2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
CountryUnited States
CitySan Diego, CA
Period6/5/116/9/11

Fingerprint

Low Voltage
Energy Efficiency
Energy efficiency
Pipelining
Pipelines
Electric potential
Sequential circuits
Flip flop circuits
Analytical Model
Multiplier
High Efficiency
High Energy
Analytical models
Silicon
Optimization
Methodology
Demonstrate
Strategy
Design
Simulation

Keywords

  • Pipeline
  • Super-pipeline
  • Ultra Low Power
  • Ultra Low Voltage

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Seok, M., Jeon, D., Chakrabarti, C., Blaauw, D., & Sylvester, D. (2011). Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design. In Proceedings - Design Automation Conference (pp. 990-995). [5982019]

Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design. / Seok, Mingoo; Jeon, Dongsuk; Chakrabarti, Chaitali; Blaauw, David; Sylvester, Dennis.

Proceedings - Design Automation Conference. 2011. p. 990-995 5982019.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Seok, M, Jeon, D, Chakrabarti, C, Blaauw, D & Sylvester, D 2011, Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design. in Proceedings - Design Automation Conference., 5982019, pp. 990-995, 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011, San Diego, CA, United States, 6/5/11.
Seok M, Jeon D, Chakrabarti C, Blaauw D, Sylvester D. Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design. In Proceedings - Design Automation Conference. 2011. p. 990-995. 5982019
Seok, Mingoo ; Jeon, Dongsuk ; Chakrabarti, Chaitali ; Blaauw, David ; Sylvester, Dennis. / Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design. Proceedings - Design Automation Conference. 2011. pp. 990-995
@inproceedings{69aae1795de2453e8c8f2cdeb0808406,
title = "Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design",
abstract = "This paper investigates pipelining methodologies for the ultra low voltage regime. Based on an analytical model and simulations, we propose a pipelining technique that provides higher energy efficiency and performance than conventional approaches to ultra low voltage design. Two-phase latch based design and sequential circuit optimizations are also proposed to further improve energy efficiency and performance. Silicon results demonstrate a 16b multiplier using the approaches in 65nm CMOS improve energy efficiency by 30{\%} and performance by 60{\%}.",
keywords = "Pipeline, Super-pipeline, Ultra Low Power, Ultra Low Voltage",
author = "Mingoo Seok and Dongsuk Jeon and Chaitali Chakrabarti and David Blaauw and Dennis Sylvester",
year = "2011",
language = "English (US)",
isbn = "9781450306362",
pages = "990--995",
booktitle = "Proceedings - Design Automation Conference",

}

TY - GEN

T1 - Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design

AU - Seok, Mingoo

AU - Jeon, Dongsuk

AU - Chakrabarti, Chaitali

AU - Blaauw, David

AU - Sylvester, Dennis

PY - 2011

Y1 - 2011

N2 - This paper investigates pipelining methodologies for the ultra low voltage regime. Based on an analytical model and simulations, we propose a pipelining technique that provides higher energy efficiency and performance than conventional approaches to ultra low voltage design. Two-phase latch based design and sequential circuit optimizations are also proposed to further improve energy efficiency and performance. Silicon results demonstrate a 16b multiplier using the approaches in 65nm CMOS improve energy efficiency by 30% and performance by 60%.

AB - This paper investigates pipelining methodologies for the ultra low voltage regime. Based on an analytical model and simulations, we propose a pipelining technique that provides higher energy efficiency and performance than conventional approaches to ultra low voltage design. Two-phase latch based design and sequential circuit optimizations are also proposed to further improve energy efficiency and performance. Silicon results demonstrate a 16b multiplier using the approaches in 65nm CMOS improve energy efficiency by 30% and performance by 60%.

KW - Pipeline

KW - Super-pipeline

KW - Ultra Low Power

KW - Ultra Low Voltage

UR - http://www.scopus.com/inward/record.url?scp=80052664256&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052664256&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:80052664256

SN - 9781450306362

SP - 990

EP - 995

BT - Proceedings - Design Automation Conference

ER -