PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference

Bo Zhang, Shihui Yin, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae Sun Seo, Mingoo Seok

Research output: Contribution to journalArticlepeer-review


This article presents a programmable in-memory computing accelerator (PIMCA) for low-precision (1&#x2013;2 b) deep neural network (DNN) inference. The custom 10T1C bitcell in the in-memory computing (IMC) macro has four additional transistors and one capacitor to perform capacitive-coupling-based multiply and accumulation (MAC) in analog-mixed-signal (AMS) domain. A macro containing <inline-formula> <tex-math notation="LaTeX">$256\ttimes 128$</tex-math> </inline-formula> bitcells can simultaneously activate all the rows, and as a result, it can perform a matrix-vector multiplication (VMM) in one cycle. PIMCA integrates 108 of such IMC static random-access memory (SRAM) macros with the custom six-stage pipeline and the custom instruction set architecture (ISA) for instruction-level programmability. The results of IMC macros are fed to a single-instruction-multiple-data (SIMD) processor for other computations such as partial sum accumulation, max-pooling, activation functions, etc. To effectively use the IMC and SIMD datapath, we customize the ISA especially by adding hardware loop support, which reduces the program size by up to 73%. The accelerator is prototyped in a 28-nm technology, and integrates a total of 3.4-Mb IMC SRAM and 1.5-Mb off-the-shelf activation SRAM, demonstrating one of the largest IMC accelerators to date. It achieves the system-level energy efficiency of 437 TOPS/W and the peak throughput of 49 TOPS at the 42-MHz clock frequency and 1-V supply for the VGG9 and the ResNet-18 on the CIFAR-10 dataset.

Original languageEnglish (US)
Pages (from-to)1-14
Number of pages14
JournalIEEE Journal of Solid-State Circuits
StateAccepted/In press - 2022
Externally publishedYes


  • Capacitive coupling computing
  • Capacitors
  • Computer architecture
  • deep neural network (DNN)
  • Hardware
  • in-memory computing (IMC)
  • Neural networks
  • programmable accelerator
  • Random access memory
  • Registers
  • Virtual machine monitors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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