PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

Shihui Yin; Bo Zhang; Minkyu Kim; Jyotishman Saikia; Soonwan Kwon; Sungmeen Myung; Hyunsoo Kim; Sang Joon Kim; Mingoo Seok; Jae Sun Seo

doi:10.23919/VLSICircuits52068.2021.9492403

PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

Shihui Yin, Bo Zhang, Minkyu Kim, Jyotishman Saikia, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Mingoo Seok, Jae Sun Seo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We present a programmable in-memory computing (IMC) accelerator integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We developed a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28nm prototype chip achieves system-level peak energy-efficiency of 437 TOPS/W and peak throughput of 4.9 TOPS at 40MHz, 1V supply.

Original language	English (US)
Title of host publication	2021 Symposium on VLSI Circuits, VLSI Circuits 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9784863487796
DOIs	https://doi.org/10.23919/VLSICircuits52068.2021.9492403
State	Published - Jun 13 2021
Externally published	Yes
Event	35th Symposium on VLSI Circuits, VLSI Circuits 2021 - Virutal, Online Duration: Jun 13 2021 → Jun 19 2021

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2021-June

Conference

Conference	35th Symposium on VLSI Circuits, VLSI Circuits 2021
City	Virutal, Online
Period	6/13/21 → 6/19/21

Keywords

custom ISA
DNN accelerator
In-memory computing

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.23919/VLSICircuits52068.2021.9492403

Cite this

Yin, S., Zhang, B., Kim, M., Saikia, J., Kwon, S., Myung, S., Kim, H., Joon Kim, S., Seok, M., & Seo, J. S. (2021). PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. In 2021 Symposium on VLSI Circuits, VLSI Circuits 2021 [9492403] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2021-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSICircuits52068.2021.9492403

PIMCA : A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. / Yin, Shihui; Zhang, Bo; Kim, Minkyu; Saikia, Jyotishman; Kwon, Soonwan; Myung, Sungmeen; Kim, Hyunsoo; Joon Kim, Sang; Seok, Mingoo; Seo, Jae Sun.

2021 Symposium on VLSI Circuits, VLSI Circuits 2021. Institute of Electrical and Electronics Engineers Inc., 2021. 9492403 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2021-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yin, S, Zhang, B, Kim, M, Saikia, J, Kwon, S, Myung, S, Kim, H, Joon Kim, S, Seok, M & Seo, JS 2021, PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. in 2021 Symposium on VLSI Circuits, VLSI Circuits 2021., 9492403, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2021-June, Institute of Electrical and Electronics Engineers Inc., 35th Symposium on VLSI Circuits, VLSI Circuits 2021, Virutal, Online, 6/13/21. https://doi.org/10.23919/VLSICircuits52068.2021.9492403

Yin S, Zhang B, Kim M, Saikia J, Kwon S, Myung S et al. PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. In 2021 Symposium on VLSI Circuits, VLSI Circuits 2021. Institute of Electrical and Electronics Engineers Inc. 2021. 9492403. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.23919/VLSICircuits52068.2021.9492403

Yin, Shihui ; Zhang, Bo ; Kim, Minkyu ; Saikia, Jyotishman ; Kwon, Soonwan ; Myung, Sungmeen ; Kim, Hyunsoo ; Joon Kim, Sang ; Seok, Mingoo ; Seo, Jae Sun. / PIMCA : A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference. 2021 Symposium on VLSI Circuits, VLSI Circuits 2021. Institute of Electrical and Electronics Engineers Inc., 2021. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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abstract = "We present a programmable in-memory computing (IMC) accelerator integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We developed a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28nm prototype chip achieves system-level peak energy-efficiency of 437 TOPS/W and peak throughput of 4.9 TOPS at 40MHz, 1V supply.",

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PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

UN SDGs

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