TY - GEN
T1 - PIMA-logic
T2 - 55th Annual Design Automation Conference, DAC 2018
AU - Angizi, Shaahin
AU - He, Zhezhi
AU - Fan, Deliang
N1 - Funding Information:
5 CONCLUSION In this paper, we proposed PIMA-Logic as a novel memory architecture to further push the boundaries of processing-in-memory so that complex bit-wise computations can be performed between locally-flexible operands (either in the same row or in the same column) within memory. The device-to-architecture simulation results show that PIMA-Logic can achieve up to 56% and 31.6% improvements with respect to overall energy and delay on large scale logic benchmarks compared to well-designed Pinatubo equally-implemented with SOT-MRAM arrays. ACKNOWLEDGEMENTS This work is supported in part by the National Science Foundation under Grant No. 1740126 and Semiconductor Research Corporation nCORE REFERENCES
PY - 2018/6/24
Y1 - 2018/6/24
N2 - In this paper, we propose PIMA-Logic, as a novel Processing-in-Memory Architecture for highly flexible and efficient Logic computation. Instead of integrating complex logic units in cost-sensitive memory, PIMA-Logic exploits a hardware-friendly approach to implement Boolean logic functions between operands either located in the same row or the same column within entire memory arrays. Furthermore, it can efficiently process more complex logic functions between multiple operands to further reduce the latency and power-hungry data movement. The proposed architecture is developed based on Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array and it can simultaneously work as a non-volatile memory and a reconfigurable in-memory logic. The device-to-architecture co-simulation results show that PIMA-Logic can achieve up to 56% and 31.6% improvements with respect to overall energy and delay on combinational logic benchmarks compared to recent Pinatubo architecture. We further implement an in-memory data encryption engine based on PIMA-Logic as a case study. With AES application, it shows 77.2% and 21% lower energy consumption compared to CMOS-ASIC and recent RIMPA implementation, respectively.
AB - In this paper, we propose PIMA-Logic, as a novel Processing-in-Memory Architecture for highly flexible and efficient Logic computation. Instead of integrating complex logic units in cost-sensitive memory, PIMA-Logic exploits a hardware-friendly approach to implement Boolean logic functions between operands either located in the same row or the same column within entire memory arrays. Furthermore, it can efficiently process more complex logic functions between multiple operands to further reduce the latency and power-hungry data movement. The proposed architecture is developed based on Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array and it can simultaneously work as a non-volatile memory and a reconfigurable in-memory logic. The device-to-architecture co-simulation results show that PIMA-Logic can achieve up to 56% and 31.6% improvements with respect to overall energy and delay on combinational logic benchmarks compared to recent Pinatubo architecture. We further implement an in-memory data encryption engine based on PIMA-Logic as a case study. With AES application, it shows 77.2% and 21% lower energy consumption compared to CMOS-ASIC and recent RIMPA implementation, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85053661580&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85053661580&partnerID=8YFLogxK
U2 - 10.1145/3195970.3196092
DO - 10.1145/3195970.3196092
M3 - Conference contribution
AN - SCOPUS:85053661580
SN - 9781450357005
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 55th Annual Design Automation Conference, DAC 2018
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 24 June 2018 through 29 June 2018
ER -