TY - GEN
T1 - PIM-Aligner
T2 - 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
AU - Angizi, Shaahin
AU - Sun, Jiao
AU - Zhang, Wei
AU - Fan, Deliang
N1 - Publisher Copyright:
© 2020 EDAA.
PY - 2020/3
Y1 - 2020/3
N2 - In this paper, we propose a high-throughput and energy-efficient Processing-in-Memory accelerator (PIM-Aligner) to execute DNA short read alignment based on an optimized and hardware-friendly alignment algorithm. We first reconstruct the existing sequence alignment algorithm based on BWT and FM-index such that it can be fully implemented in PIM platforms. It supports exact alignment and also handles mismatches to reduce excessive backtracking. We then develop PIM-Aligner platform that transforms SOT-MRAM array to a potential computational memory to accelerate the reconstructed alignment-in-memory algorithm incurring a low cost on top of original SOT-MRAM chips (less than 10% of chip area). Accordingly, we present a local data partitioning, mapping, and pipeline technique to maximize the parallelism in multiple computational sub-array while doing the alignment task. The simulation results show that PIM-Aligner outperforms recent platforms based on dynamic programming with ∼ 3.1× higher throughput per Watt. Besides, PIM-Aligner improves the short read alignment throughput per Watt per mm2 by ∼ 9× and 1.9× compared to FM-index-based ASIC and processing-in-ReRAM designs, respectively.
AB - In this paper, we propose a high-throughput and energy-efficient Processing-in-Memory accelerator (PIM-Aligner) to execute DNA short read alignment based on an optimized and hardware-friendly alignment algorithm. We first reconstruct the existing sequence alignment algorithm based on BWT and FM-index such that it can be fully implemented in PIM platforms. It supports exact alignment and also handles mismatches to reduce excessive backtracking. We then develop PIM-Aligner platform that transforms SOT-MRAM array to a potential computational memory to accelerate the reconstructed alignment-in-memory algorithm incurring a low cost on top of original SOT-MRAM chips (less than 10% of chip area). Accordingly, we present a local data partitioning, mapping, and pipeline technique to maximize the parallelism in multiple computational sub-array while doing the alignment task. The simulation results show that PIM-Aligner outperforms recent platforms based on dynamic programming with ∼ 3.1× higher throughput per Watt. Besides, PIM-Aligner improves the short read alignment throughput per Watt per mm2 by ∼ 9× and 1.9× compared to FM-index-based ASIC and processing-in-ReRAM designs, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85087423368&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85087423368&partnerID=8YFLogxK
U2 - 10.23919/DATE48585.2020.9116303
DO - 10.23919/DATE48585.2020.9116303
M3 - Conference contribution
AN - SCOPUS:85087423368
T3 - Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
SP - 1265
EP - 1270
BT - Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
A2 - Di Natale, Giorgio
A2 - Bolchini, Cristiana
A2 - Vatajelu, Elena-Ioana
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 March 2020 through 13 March 2020
ER -