This paper describes a low voltage physically unclonable function (PUF) implemented with SRAM circuits. The approach allows the use of foundry cells, which are used in this paper, and requires very minor modifications to standard SRAM arrays. The PUF functionality is designed into large 1M-bit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts. The low variability foundry process produces good PUF results, demonstrating that the approach should also be good on conventional processes, since greater mismatch should positively impact PUF performance as measured by code word stability. The impact of process corners is also experimentally determined. Unstable bits, which we attribute to random telegraph noise is shown to be at manageable levels. We describe the circuit operation, statistical behavior, and suggest helper data functions that allow operation without error correction. This is important since error correction necessarily allows some leakage of the underlying secret codes.
|Original language||English (US)|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Accepted/In press - Jan 1 2018|
- Error correction codes
- Integrated circuits
- physically unclonable functions
- random telegraph noise.
- SRAM cells
- SRAM variability
- Static random access memory
ASJC Scopus subject areas
- Electrical and Electronic Engineering