TY - JOUR
T1 - Physically unclonable functions using foundry SRAM cells
AU - Clark, Lawrence T
AU - Medapuram, Sai Bharadwaj
AU - Kadiyala, Divya Kiran
AU - Brunhaver, John
N1 - Funding Information:
Manuscript received March 20, 2018; revised June 25, 2018 and August 29, 2018; accepted September 25, 2018. Date of publication October 19, 2018; date of current version February 5, 2019. This work was supported in part by the Fujitsu Corporation and in part by the Space Micro Corporation. This paper was recommended by Associate Editor Y. Pu. (Corresponding author: Lawrence T. Clark.) L. T. Clark, S. B. Medapuram, and J. Brunhaver are with the School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: lawrence.clark@asu.edu; bmedapur@asu.edu; john.brunhaver@asu.edu).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2019/3
Y1 - 2019/3
N2 - This paper describes a low voltage physically unclonable function (PUF) implemented with SRAM circuits. The approach allows the use of foundry cells, which are used in this paper, and requires very minor modifications to standard SRAM arrays. The PUF functionality is designed into large 1M-bit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts. The low variability foundry process produces good PUF results, demonstrating that the approach should also be good on conventional processes, since greater mismatch should positively impact PUF performance as measured by code word stability. The impact of process corners is also experimentally determined. Unstable bits, which we attribute to random telegraph noise is shown to be at manageable levels. We describe the circuit operation, statistical behavior, and suggest helper data functions that allow operation without error correction. This is important since error correction necessarily allows some leakage of the underlying secret codes.
AB - This paper describes a low voltage physically unclonable function (PUF) implemented with SRAM circuits. The approach allows the use of foundry cells, which are used in this paper, and requires very minor modifications to standard SRAM arrays. The PUF functionality is designed into large 1M-bit SRAM arrays fabricated on a 55-nm process using the foundry supplied SRAM cell layouts. The low variability foundry process produces good PUF results, demonstrating that the approach should also be good on conventional processes, since greater mismatch should positively impact PUF performance as measured by code word stability. The impact of process corners is also experimentally determined. Unstable bits, which we attribute to random telegraph noise is shown to be at manageable levels. We describe the circuit operation, statistical behavior, and suggest helper data functions that allow operation without error correction. This is important since error correction necessarily allows some leakage of the underlying secret codes.
KW - SRAM variability
KW - Static random access memory
KW - physically unclonable functions
KW - random telegraph noise
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U2 - 10.1109/TCSI.2018.2873777
DO - 10.1109/TCSI.2018.2873777
M3 - Article
AN - SCOPUS:85055200241
VL - 66
SP - 955
EP - 966
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 3
M1 - 8500746
ER -