Physical-aware link allocation and route assignment for chip multiprocessing

Nikita Nikitin, Satrajit Chatterjee, Jordi Cortadella, Mike Kishinevsky, Umit Ogras

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining the topology of the network and the message routes for the traffic among the processing elements of the system. The solution of the problem meets the physical and performance constraints defined by the designer. The method guarantees that the generated solution is deadlock free. It is also capable of automatically discovering topologies that have been previously used in industrial systems. The applicability of the method has been validated by solving realistic size interconnect networks modeling the typical multiprocessor systems.

Original languageEnglish (US)
Title of host publicationNOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip
Pages125-134
Number of pages10
DOIs
StatePublished - 2010
Externally publishedYes
Event4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010 - Grenoble, France
Duration: May 3 2010May 6 2010

Other

Other4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010
CountryFrance
CityGrenoble
Period5/3/105/6/10

Fingerprint

Topology
Processing
System-on-chip

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Nikitin, N., Chatterjee, S., Cortadella, J., Kishinevsky, M., & Ogras, U. (2010). Physical-aware link allocation and route assignment for chip multiprocessing. In NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip (pp. 125-134). [5507555] https://doi.org/10.1109/NOCS.2010.22

Physical-aware link allocation and route assignment for chip multiprocessing. / Nikitin, Nikita; Chatterjee, Satrajit; Cortadella, Jordi; Kishinevsky, Mike; Ogras, Umit.

NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. 2010. p. 125-134 5507555.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nikitin, N, Chatterjee, S, Cortadella, J, Kishinevsky, M & Ogras, U 2010, Physical-aware link allocation and route assignment for chip multiprocessing. in NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip., 5507555, pp. 125-134, 4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010, Grenoble, France, 5/3/10. https://doi.org/10.1109/NOCS.2010.22
Nikitin N, Chatterjee S, Cortadella J, Kishinevsky M, Ogras U. Physical-aware link allocation and route assignment for chip multiprocessing. In NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. 2010. p. 125-134. 5507555 https://doi.org/10.1109/NOCS.2010.22
Nikitin, Nikita ; Chatterjee, Satrajit ; Cortadella, Jordi ; Kishinevsky, Mike ; Ogras, Umit. / Physical-aware link allocation and route assignment for chip multiprocessing. NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. 2010. pp. 125-134
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