TY - GEN
T1 - Physical-aware link allocation and route assignment for chip multiprocessing
AU - Nikitin, Nikita
AU - Chatterjee, Satrajit
AU - Cortadella, Jordi
AU - Kishinevsky, Mike
AU - Ogras, Umit
N1 - Copyright:
Copyright 2010 Elsevier B.V., All rights reserved.
PY - 2010
Y1 - 2010
N2 - The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining the topology of the network and the message routes for the traffic among the processing elements of the system. The solution of the problem meets the physical and performance constraints defined by the designer. The method guarantees that the generated solution is deadlock free. It is also capable of automatically discovering topologies that have been previously used in industrial systems. The applicability of the method has been validated by solving realistic size interconnect networks modeling the typical multiprocessor systems.
AB - The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining the topology of the network and the message routes for the traffic among the processing elements of the system. The solution of the problem meets the physical and performance constraints defined by the designer. The method guarantees that the generated solution is deadlock free. It is also capable of automatically discovering topologies that have been previously used in industrial systems. The applicability of the method has been validated by solving realistic size interconnect networks modeling the typical multiprocessor systems.
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U2 - 10.1109/NOCS.2010.22
DO - 10.1109/NOCS.2010.22
M3 - Conference contribution
AN - SCOPUS:77955119126
SN - 9780769540535
T3 - NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip
SP - 125
EP - 134
BT - NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip
T2 - 4th ACM/IEEE International Symposium on Networks on Chip, NOCS 2010
Y2 - 3 May 2010 through 6 May 2010
ER -