A methodology to analyze device-to-circuit characteristics and predict memory array performance is presented. With a five- parameter characterization of the selection device and a compact model of RRAM, we are able to capture the behaviors of reported selection devices and simulate 1S1R cell/array performance with RRAM compact modeling using HSPICE. To predict the performance of the memory array for a variety of selectors, machine-learning algorithms are employed, using device characteristics and circuit simulation results as the training data. The influence of selector parameters on the 1S1R cell and array behavior is investigated and projected to large Gbit arrays. The machine learning methods enable time-efficient and accurate estimates of 1S1R array performance to guide large-scale memory design.