Performance Prediction of Large-Scale 1S1R Resistive Memory Array Using Machine Learning

Zizhen Jiang, Peng Huang, Liang Zhao, Shahar Kvatinsky, Shimeng Yu, Xiaoyan Liu, Jinfeng Kang, Yoshio Nishi, H. S Philip Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations


A methodology to analyze device-to-circuit characteristics and predict memory array performance is presented. With a five- parameter characterization of the selection device and a compact model of RRAM, we are able to capture the behaviors of reported selection devices and simulate 1S1R cell/array performance with RRAM compact modeling using HSPICE. To predict the performance of the memory array for a variety of selectors, machine-learning algorithms are employed, using device characteristics and circuit simulation results as the training data. The influence of selector parameters on the 1S1R cell and array behavior is investigated and projected to large Gbit arrays. The machine learning methods enable time-efficient and accurate estimates of 1S1R array performance to guide large-scale memory design.

Original languageEnglish (US)
Title of host publication2015 IEEE 7th International Memory Workshop, IMW 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781467369312
StatePublished - Jul 2 2015
Event2015 7th IEEE International Memory Workshop, IMW 2015 - Monterey, United States
Duration: May 17 2015May 20 2015


Other2015 7th IEEE International Memory Workshop, IMW 2015
CountryUnited States


  • 1S1R
  • crossbar array
  • machine learning
  • prediction
  • RRAM
  • selector

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering
  • Computer Science Applications

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