Performance optimal processor throttling under thermal constraints

Ravishankar Rao, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

37 Scopus citations

Abstract

We derive analytically, the performance optimal throttling curve for a processor under thermal constraints for a given task sequence. We found that keeping the chip temperature constant requires an exponential speed curve. Earlier works that propose constant throttling only keep the package/case temperature constant, and are hence suboptimal. We develop high-level thermal and power models that are simple enough for analysis, yet account for important effects like the power-density variation across a chip (hotspots), leakage dependence on temperature (LDT), and differing thermal characteristics of the silicon die and the thermal solution. We use a piecewise-linear approximation for the exponential leakage dependence on temperature, and devise a method to remove the circular dependency between leakage power and temperature. To solve the multi-task speed control problem, we first solve analytically, the single task problem with a constraint on the final package temperature using optimal control theory. We then find the optimum final package temperature of each task by dynamic programming. We compared the total execution time of several randomly generated task sequences using the optimal control policy against a constant speed throttling policy, and found significantly smaller total execution times. We compared the thermal profiles predicted by the proposed high-level thermal model to that of the Hotspot thermal model, and found them to be in good agreement.

Original languageEnglish (US)
Title of host publicationCASES'07
Subtitle of host publicationProceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
Pages257-266
Number of pages10
DOIs
StatePublished - Dec 1 2007
EventCASES'07: 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems - Salzburg, Austria
Duration: Sep 30 2007Oct 3 2007

Publication series

NameCASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Other

OtherCASES'07: 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
CountryAustria
CitySalzburg
Period9/30/0710/3/07

Keywords

  • Leakage dependence on temperature
  • Power
  • Thermal management
  • Thermal model
  • Throttling

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

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  • Cite this

    Rao, R., & Vrudhula, S. (2007). Performance optimal processor throttling under thermal constraints. In CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (pp. 257-266). (CASES'07: Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems). https://doi.org/10.1145/1289881.1289925