Performance and resource optimization of NoC router architecture for master and slave IP cores

Glenn Leary, Krishna Mehta, Karam S. Chatha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized NoC router architecture that can be optimized for performance and resource requirement by exploiting the master or slave behavior of the cores that are attached to it. We implemented the proposed router architecture for the IBM Coreconnect protocol and mapped it on the Xilinx Virtex series FPGA. We compared the FPGA based implementation against industry strength bus design that supports the IBM Coreconnect protocol, namely processor local bus (PLB). For similar resource requirements, our design demonstrated a 97.6% increase in throughput and 76.53% decrease in latency in comparison to the PLB. We also compared the proposed architecture with an existing NoC router design that is oblivious to master/slave IP cores. In the case of a router with all shared slaves our design resulted in 65.9% reduction in resources, 548% increase in throughput and 84.7% reduction in latency.

Original languageEnglish (US)
Title of host publicationCODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis
Pages155-160
Number of pages6
DOIs
StatePublished - 2007
EventCODES+ISSS 2007: 5th International Conference on Hardware/Software Codesign and System Synthesis - Salzburg, Austria
Duration: Sep 30 2007Oct 3 2007

Other

OtherCODES+ISSS 2007: 5th International Conference on Hardware/Software Codesign and System Synthesis
CountryAustria
CitySalzburg
Period9/30/0710/3/07

Fingerprint

Routers
Field programmable gate arrays (FPGA)
Throughput
Network-on-chip
Intellectual property core
Communication
Industry

Keywords

  • FPGA
  • Network-on-chip

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Software

Cite this

Leary, G., Mehta, K., & Chatha, K. S. (2007). Performance and resource optimization of NoC router architecture for master and slave IP cores. In CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis (pp. 155-160) https://doi.org/10.1145/1289816.1289856

Performance and resource optimization of NoC router architecture for master and slave IP cores. / Leary, Glenn; Mehta, Krishna; Chatha, Karam S.

CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis. 2007. p. 155-160.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Leary, G, Mehta, K & Chatha, KS 2007, Performance and resource optimization of NoC router architecture for master and slave IP cores. in CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis. pp. 155-160, CODES+ISSS 2007: 5th International Conference on Hardware/Software Codesign and System Synthesis, Salzburg, Austria, 9/30/07. https://doi.org/10.1145/1289816.1289856
Leary G, Mehta K, Chatha KS. Performance and resource optimization of NoC router architecture for master and slave IP cores. In CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis. 2007. p. 155-160 https://doi.org/10.1145/1289816.1289856
Leary, Glenn ; Mehta, Krishna ; Chatha, Karam S. / Performance and resource optimization of NoC router architecture for master and slave IP cores. CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis. 2007. pp. 155-160
@inproceedings{d1efb8c230cc4c11b610a85f2dc1db86,
title = "Performance and resource optimization of NoC router architecture for master and slave IP cores",
abstract = "System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized NoC router architecture that can be optimized for performance and resource requirement by exploiting the master or slave behavior of the cores that are attached to it. We implemented the proposed router architecture for the IBM Coreconnect protocol and mapped it on the Xilinx Virtex series FPGA. We compared the FPGA based implementation against industry strength bus design that supports the IBM Coreconnect protocol, namely processor local bus (PLB). For similar resource requirements, our design demonstrated a 97.6{\%} increase in throughput and 76.53{\%} decrease in latency in comparison to the PLB. We also compared the proposed architecture with an existing NoC router design that is oblivious to master/slave IP cores. In the case of a router with all shared slaves our design resulted in 65.9{\%} reduction in resources, 548{\%} increase in throughput and 84.7{\%} reduction in latency.",
keywords = "FPGA, Network-on-chip",
author = "Glenn Leary and Krishna Mehta and Chatha, {Karam S.}",
year = "2007",
doi = "10.1145/1289816.1289856",
language = "English (US)",
isbn = "9781595938244",
pages = "155--160",
booktitle = "CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis",

}

TY - GEN

T1 - Performance and resource optimization of NoC router architecture for master and slave IP cores

AU - Leary, Glenn

AU - Mehta, Krishna

AU - Chatha, Karam S.

PY - 2007

Y1 - 2007

N2 - System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized NoC router architecture that can be optimized for performance and resource requirement by exploiting the master or slave behavior of the cores that are attached to it. We implemented the proposed router architecture for the IBM Coreconnect protocol and mapped it on the Xilinx Virtex series FPGA. We compared the FPGA based implementation against industry strength bus design that supports the IBM Coreconnect protocol, namely processor local bus (PLB). For similar resource requirements, our design demonstrated a 97.6% increase in throughput and 76.53% decrease in latency in comparison to the PLB. We also compared the proposed architecture with an existing NoC router design that is oblivious to master/slave IP cores. In the case of a router with all shared slaves our design resulted in 65.9% reduction in resources, 548% increase in throughput and 84.7% reduction in latency.

AB - System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized NoC router architecture that can be optimized for performance and resource requirement by exploiting the master or slave behavior of the cores that are attached to it. We implemented the proposed router architecture for the IBM Coreconnect protocol and mapped it on the Xilinx Virtex series FPGA. We compared the FPGA based implementation against industry strength bus design that supports the IBM Coreconnect protocol, namely processor local bus (PLB). For similar resource requirements, our design demonstrated a 97.6% increase in throughput and 76.53% decrease in latency in comparison to the PLB. We also compared the proposed architecture with an existing NoC router design that is oblivious to master/slave IP cores. In the case of a router with all shared slaves our design resulted in 65.9% reduction in resources, 548% increase in throughput and 84.7% reduction in latency.

KW - FPGA

KW - Network-on-chip

UR - http://www.scopus.com/inward/record.url?scp=38849183295&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=38849183295&partnerID=8YFLogxK

U2 - 10.1145/1289816.1289856

DO - 10.1145/1289816.1289856

M3 - Conference contribution

AN - SCOPUS:38849183295

SN - 9781595938244

SP - 155

EP - 160

BT - CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis

ER -