TY - GEN
T1 - Pathfinding for 22nm CMOS designs using Predictive Technology Models
AU - Li, Xia
AU - Zhao, Wei
AU - Cao, Yu
AU - Zhu, Zhi
AU - Song, Jooyoung
AU - Bang, David
AU - Wang, Chi Chao
AU - Kang, Seung H.
AU - Wang, Joseph
AU - Nowak, Matt
AU - Yu, Nick
PY - 2009
Y1 - 2009
N2 - Traditional IC scaling is becoming increasingly difficult at the 22nm node and beyond. Dealing with these challenges increase product development cycle time. For continued CMOS scaling, it is essential to start design explorations in new process nodes as early as possible. Such an effort requires having Predictive Technology Models, which bridge technological and design practices, in order to assess the performance impact of future key modules. In this paper we propose a strategy that enables simultaneous investigation of advanced process and design concepts. Based on a customized predictive methodology and silicon data at 90-45nm nodes, compact transistor and interconnect models are developed for the next generation CMOS technology. We capture the heuristic device behavior during the scaling, which helps us to gain key insights that allow us to make tradeoffs of circuit performance metrics for next technology node.
AB - Traditional IC scaling is becoming increasingly difficult at the 22nm node and beyond. Dealing with these challenges increase product development cycle time. For continued CMOS scaling, it is essential to start design explorations in new process nodes as early as possible. Such an effort requires having Predictive Technology Models, which bridge technological and design practices, in order to assess the performance impact of future key modules. In this paper we propose a strategy that enables simultaneous investigation of advanced process and design concepts. Based on a customized predictive methodology and silicon data at 90-45nm nodes, compact transistor and interconnect models are developed for the next generation CMOS technology. We capture the heuristic device behavior during the scaling, which helps us to gain key insights that allow us to make tradeoffs of circuit performance metrics for next technology node.
UR - http://www.scopus.com/inward/record.url?scp=74049129900&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=74049129900&partnerID=8YFLogxK
U2 - 10.1109/CICC.2009.5280845
DO - 10.1109/CICC.2009.5280845
M3 - Conference contribution
AN - SCOPUS:74049129900
SN - 9781424440726
T3 - Proceedings of the Custom Integrated Circuits Conference
SP - 227
EP - 230
BT - 2009 IEEE Custom Integrated Circuits Conference, CICC '09
T2 - 2009 IEEE Custom Integrated Circuits Conference, CICC '09
Y2 - 13 September 2009 through 16 September 2009
ER -