Pathfinding for 22nm CMOS designs using Predictive Technology Models

Xia Li, Wei Zhao, Yu Cao, Zhi Zhu, Jooyoung Song, David Bang, Chi Chao Wang, Seung H. Kang, Joseph Wang, Matt Nowak, Nick Yu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Traditional IC scaling is becoming increasingly difficult at the 22nm node and beyond. Dealing with these challenges increase product development cycle time. For continued CMOS scaling, it is essential to start design explorations in new process nodes as early as possible. Such an effort requires having Predictive Technology Models, which bridge technological and design practices, in order to assess the performance impact of future key modules. In this paper we propose a strategy that enables simultaneous investigation of advanced process and design concepts. Based on a customized predictive methodology and silicon data at 90-45nm nodes, compact transistor and interconnect models are developed for the next generation CMOS technology. We capture the heuristic device behavior during the scaling, which helps us to gain key insights that allow us to make tradeoffs of circuit performance metrics for next technology node.

Original languageEnglish (US)
Title of host publicationProceedings of the Custom Integrated Circuits Conference
Pages227-230
Number of pages4
DOIs
StatePublished - 2009
Event2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States
Duration: Sep 13 2009Sep 16 2009

Other

Other2009 IEEE Custom Integrated Circuits Conference, CICC '09
CountryUnited States
CitySan Jose, CA
Period9/13/099/16/09

Fingerprint

Product development
Transistors
Silicon
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Li, X., Zhao, W., Cao, Y., Zhu, Z., Song, J., Bang, D., ... Yu, N. (2009). Pathfinding for 22nm CMOS designs using Predictive Technology Models. In Proceedings of the Custom Integrated Circuits Conference (pp. 227-230). [5280845] https://doi.org/10.1109/CICC.2009.5280845

Pathfinding for 22nm CMOS designs using Predictive Technology Models. / Li, Xia; Zhao, Wei; Cao, Yu; Zhu, Zhi; Song, Jooyoung; Bang, David; Wang, Chi Chao; Kang, Seung H.; Wang, Joseph; Nowak, Matt; Yu, Nick.

Proceedings of the Custom Integrated Circuits Conference. 2009. p. 227-230 5280845.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, X, Zhao, W, Cao, Y, Zhu, Z, Song, J, Bang, D, Wang, CC, Kang, SH, Wang, J, Nowak, M & Yu, N 2009, Pathfinding for 22nm CMOS designs using Predictive Technology Models. in Proceedings of the Custom Integrated Circuits Conference., 5280845, pp. 227-230, 2009 IEEE Custom Integrated Circuits Conference, CICC '09, San Jose, CA, United States, 9/13/09. https://doi.org/10.1109/CICC.2009.5280845
Li X, Zhao W, Cao Y, Zhu Z, Song J, Bang D et al. Pathfinding for 22nm CMOS designs using Predictive Technology Models. In Proceedings of the Custom Integrated Circuits Conference. 2009. p. 227-230. 5280845 https://doi.org/10.1109/CICC.2009.5280845
Li, Xia ; Zhao, Wei ; Cao, Yu ; Zhu, Zhi ; Song, Jooyoung ; Bang, David ; Wang, Chi Chao ; Kang, Seung H. ; Wang, Joseph ; Nowak, Matt ; Yu, Nick. / Pathfinding for 22nm CMOS designs using Predictive Technology Models. Proceedings of the Custom Integrated Circuits Conference. 2009. pp. 227-230
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