Path-based, randomized, oblivious, minimal routing

Myong Hyon Cho, Mieszko Lis, Keun Sup Shim, Michel Kinsy, Srinivas Devadas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Abstract

Path-based, Randomized, Oblivious, Minimal routing (PROM) is a family of oblivious, minimal, path-diverse routing algorithms especially suitable for Network-on-Chip applications with n x n mesh geometry. Rather than choosing among all possible paths at the source node, PROM algorithms achieve the same effect progressively through efficient, local randomized decisions at each hop. Routing is deadlock-free in all PROM algorithms when the routers have at least two virtual channels. While the approach we present can be viewed as a generalization of both ROMM and O1TURN routing, it combines the low-hardware cost of O1TURN with the routing diversity offered by the most complex n-phase ROMM schemes. As all PROM algorithms employ the same hardware, a wide range of routing behaviors, from O1TURN-equivalent to uniformly path-diverse, can be effected by adjusting just one parameter, even while the network is live and continues to forward packets. Detailed simulation on a set of benchmarks indicates that, on equivalent hardware, the performance of PROM algorithms compares favorably to existing oblivious routing algorithms, including dimension-ordered routing, two-phase ROMM, and O1TURN.

Original languageEnglish (US)
Title of host publication2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42
Pages23-28
Number of pages6
DOIs
StatePublished - 2009
Externally publishedYes
Event2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42 - New York, NY, United States
Duration: Dec 12 2009Dec 12 2009

Publication series

Name2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42

Conference

Conference2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42
Country/TerritoryUnited States
CityNew York, NY
Period12/12/0912/12/09

Keywords

  • C.2.1 [network architecture and design]: network communications

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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