Abstract
With advances in process technology, soft errors are becoming an increasingly critical design concern. Owing to their large area, high density, and low operating voltages, caches are worst hit by soft errors. Based on the observation that in multimedia applications, not all data require the same amount of protection from soft errors, we propose a partially protected cache (PPC) architecture, in which there are two caches, one protected and the other unprotected at the same level of memory hierarchy. We demonstrate that as compared to the existing unprotected cache architectures, PPC architectures can provide 47 times reduction in failure rate, at only 1% runtime and 3% power overheads. In addition, the failure rate reduction obtained by PPCs is very sensitive to the PPC cache configuration. Therefore, this observation provides an opportunity for further improvement of the solution by correctly parameterizing the PPC configurations. Consequently, we develop design space exploration (DSE) strategies to discover the best PPC configuration. Our DSE technique can reduce the exploration time by more than six times as compared to an exhaustive approach.
| Original language | English (US) |
|---|---|
| Article number | 4799213 |
| Pages (from-to) | 1343-1347 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 17 |
| Issue number | 9 |
| DOIs | |
| State | Published - Sep 2009 |
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Keywords
- Memory fault tolerance
- Multimedia embedded systems
- Partially protected cache (PPC)
- Soft error
- Unequal data protection
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
- Software
Cite this
Partially protected caches to reduce failures due to soft errors in multimedia applications. / Lee, Kyoungwoo; Shrivastava, Aviral; Issenin, Ilya; Dutt, Nikil; Venkatasubramanian, Nalini.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 9, 4799213, 09.2009, p. 1343-1347.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Partially protected caches to reduce failures due to soft errors in multimedia applications
AU - Lee, Kyoungwoo
AU - Shrivastava, Aviral
AU - Issenin, Ilya
AU - Dutt, Nikil
AU - Venkatasubramanian, Nalini
PY - 2009/9
Y1 - 2009/9
N2 - With advances in process technology, soft errors are becoming an increasingly critical design concern. Owing to their large area, high density, and low operating voltages, caches are worst hit by soft errors. Based on the observation that in multimedia applications, not all data require the same amount of protection from soft errors, we propose a partially protected cache (PPC) architecture, in which there are two caches, one protected and the other unprotected at the same level of memory hierarchy. We demonstrate that as compared to the existing unprotected cache architectures, PPC architectures can provide 47 times reduction in failure rate, at only 1% runtime and 3% power overheads. In addition, the failure rate reduction obtained by PPCs is very sensitive to the PPC cache configuration. Therefore, this observation provides an opportunity for further improvement of the solution by correctly parameterizing the PPC configurations. Consequently, we develop design space exploration (DSE) strategies to discover the best PPC configuration. Our DSE technique can reduce the exploration time by more than six times as compared to an exhaustive approach.
AB - With advances in process technology, soft errors are becoming an increasingly critical design concern. Owing to their large area, high density, and low operating voltages, caches are worst hit by soft errors. Based on the observation that in multimedia applications, not all data require the same amount of protection from soft errors, we propose a partially protected cache (PPC) architecture, in which there are two caches, one protected and the other unprotected at the same level of memory hierarchy. We demonstrate that as compared to the existing unprotected cache architectures, PPC architectures can provide 47 times reduction in failure rate, at only 1% runtime and 3% power overheads. In addition, the failure rate reduction obtained by PPCs is very sensitive to the PPC cache configuration. Therefore, this observation provides an opportunity for further improvement of the solution by correctly parameterizing the PPC configurations. Consequently, we develop design space exploration (DSE) strategies to discover the best PPC configuration. Our DSE technique can reduce the exploration time by more than six times as compared to an exhaustive approach.
KW - Memory fault tolerance
KW - Multimedia embedded systems
KW - Partially protected cache (PPC)
KW - Soft error
KW - Unequal data protection
UR - http://www.scopus.com/inward/record.url?scp=69649088001&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=69649088001&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2008.2002427
DO - 10.1109/TVLSI.2008.2002427
M3 - Article
AN - SCOPUS:69649088001
VL - 17
SP - 1343
EP - 1347
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 9
M1 - 4799213
ER -