Parasitic-aware synthesis of RF CMOS switching power amplifiers

Kiyong Choi, David J. Allstot, Sayfe Kiaei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Parasitic-aware synthesis and optimization techniques are presented for a 0.35μm CMOS three-stage 1W 900MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25dB gain with 49% drain efficiency from a 3.3V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Volume1
StatePublished - 2002
Event2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
Duration: May 26 2002May 29 2002

Other

Other2002 IEEE International Symposium on Circuits and Systems
CountryUnited States
CityPhoenix, AZ
Period5/26/025/29/02

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Choi, K., Allstot, D. J., & Kiaei, S. (2002). Parasitic-aware synthesis of RF CMOS switching power amplifiers. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 1)