PARAMETRIC TESTING TO LINK DESIGN AND FABRICATION.

A. Gribben, J. M. Robertson, A. J. Walton

Research output: Contribution to journalConference article

Abstract

Parametric testing is currently carried out at the end of the wafer fabrication process to determine whether or not the process is within specification. These parameters are measured on drop-in test die and an assessment is then made as to whether the wafer will yield working circuits. Typically, sheet resistances, oxide capacitances, contact resistances and threshold voltages are monitored. Usually, only a value well out of specification indicates a nonworking wafer and the precise effect on the operation of the circuits, in terms of output drive currents and speed of switching is unknown. By measuring parameters for the SPICE model, they can be used for both process control and circuit simulation, since they physically represent different aspects of device operation and can be used in the model to accurately simulate devices.

Original languageEnglish (US)
Pages (from-to)3. 1-3. 3
JournalIEE Colloquium (Digest)
Issue number1987 /12
StatePublished - Dec 1 1987

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ASJC Scopus subject areas

  • Engineering(all)
  • Electrical and Electronic Engineering

Cite this

Gribben, A., Robertson, J. M., & Walton, A. J. (1987). PARAMETRIC TESTING TO LINK DESIGN AND FABRICATION. IEE Colloquium (Digest), (1987 /12), 3. 1-3. 3.