TY - GEN
T1 - Parallel high throughput soft-output sphere decoder
AU - Qi, Q.
AU - Chakrabarti, Chaitali
PY - 2010/12/27
Y1 - 2010/12/27
N2 - Multiple-Input-Multiple-Output communication systems demand fast sphere decoding with high performance. We propose a high throughput soft-output fixed complexity sphere decoder (PFSD) that is parallel and has comparable performance to list fixed complexity sphere decoder (LFSD) and K-best sphere decoder. In addition, we propose a parallel QR decomposition algorithm to lower the preprocessing overhead, and a low complexity LLR algorithm to allow parallel update of LLR values. We demonstrate the BER and computation complexity advantages of the PFSD algorithm in a 4x4 16-QAM system. The PFSD algorithm has been mapped onto Xilinx XC4VLX160 FPGA. The resulting PFSD decoder can produce 8 candidate vectors per clock cycle, and achieve upto 75Mbps throughput for 4x4 64-QAM configuration at 100MHz with low control overhead.
AB - Multiple-Input-Multiple-Output communication systems demand fast sphere decoding with high performance. We propose a high throughput soft-output fixed complexity sphere decoder (PFSD) that is parallel and has comparable performance to list fixed complexity sphere decoder (LFSD) and K-best sphere decoder. In addition, we propose a parallel QR decomposition algorithm to lower the preprocessing overhead, and a low complexity LLR algorithm to allow parallel update of LLR values. We demonstrate the BER and computation complexity advantages of the PFSD algorithm in a 4x4 16-QAM system. The PFSD algorithm has been mapped onto Xilinx XC4VLX160 FPGA. The resulting PFSD decoder can produce 8 candidate vectors per clock cycle, and achieve upto 75Mbps throughput for 4x4 64-QAM configuration at 100MHz with low control overhead.
KW - FPGA
KW - Parallel implementation
KW - Sphere decoding
UR - http://www.scopus.com/inward/record.url?scp=78650343748&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78650343748&partnerID=8YFLogxK
U2 - 10.1109/SIPS.2010.5624783
DO - 10.1109/SIPS.2010.5624783
M3 - Conference contribution
AN - SCOPUS:78650343748
SN - 9781424489336
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
SP - 174
EP - 179
BT - 2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - Proceedings
T2 - 2010 IEEE Workshop on Signal Processing Systems, SiPS 2010
Y2 - 6 October 2010 through 8 October 2010
ER -