TY - GEN
T1 - Parallel deblocking filter for H.264 AVC/SVC
AU - Vijay, S.
AU - Chakrabarti, Chaitali
AU - Karam, Lina
PY - 2010/12/27
Y1 - 2010/12/27
N2 - This paper presents a parallel and scalable solution for adaptive deblocking filtering in H.264/AVC. While traditionally in deblocking filtering, the edges in a macroblock are processed in a sequential order, this paper demonstrates how algorithm modifications can be used to enable processing multiple consecutive edges at the same time. The proposed method increases the throughput in proportion to the number of edges that are being processed simultaneously without affecting the PSNR and bit-rate. Details of the method to process 2 consecutive edges in parallel as well as extensions to process 4 and 8 consecutive edges, are provided. A dedicated hardware architecture to process 2 edges is presented along with synthesis results. The architecture achieves a 2x increase in throughput at the expense of a 2.2x increase in area and a 1.23x increase in power.
AB - This paper presents a parallel and scalable solution for adaptive deblocking filtering in H.264/AVC. While traditionally in deblocking filtering, the edges in a macroblock are processed in a sequential order, this paper demonstrates how algorithm modifications can be used to enable processing multiple consecutive edges at the same time. The proposed method increases the throughput in proportion to the number of edges that are being processed simultaneously without affecting the PSNR and bit-rate. Details of the method to process 2 consecutive edges in parallel as well as extensions to process 4 and 8 consecutive edges, are provided. A dedicated hardware architecture to process 2 edges is presented along with synthesis results. The architecture achieves a 2x increase in throughput at the expense of a 2.2x increase in area and a 1.23x increase in power.
KW - Deblocking filter
KW - Parallel architecture
UR - http://www.scopus.com/inward/record.url?scp=78650325284&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78650325284&partnerID=8YFLogxK
U2 - 10.1109/SIPS.2010.5624773
DO - 10.1109/SIPS.2010.5624773
M3 - Conference contribution
AN - SCOPUS:78650325284
SN - 9781424489336
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
SP - 116
EP - 121
BT - 2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - Proceedings
T2 - 2010 IEEE Workshop on Signal Processing Systems, SiPS 2010
Y2 - 6 October 2010 through 8 October 2010
ER -