Parallel architecture for large scale production systems

K. W. Hwang, J. Tan, J. H. Wang, J. Srivastava, W. T. Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The authors present an architecture, suitable for implementation on a shared memory multiprocessor system, in which all the phases can run in parallel. Running multiple match, execution, and select phases causes subtle synchronization problems, which if not resolved can lead to altered semantics. The proposed architecture uses a lock and interference manager and a scheduler to resolve the possible synchronization conflicts. A new lock which provides concurrency beyond the standard two-phase locking in databases is used. The conflict resolution phase has been formalized as a scheduling problem. The approach taken is conservative in the sense that the scheduler performs careful analysis (interference avoidance and abort avoidance tests) to prevent interference, abort, and blocking.

Original languageEnglish (US)
Title of host publicationIEEE Int Workshop Tools Artif Intell Archit Lang Algorithms
Editors Anon
PublisherPubl by IEEE
Pages27-33
Number of pages7
ISBN (Print)0818619848
StatePublished - Dec 1 1989
EventIEEE International Workshop on Tools for Artificial Intelligence: Architectures, Languages and Algorithms - Fairfax, VA, USA
Duration: Oct 23 1989Oct 25 1989

Publication series

NameIEEE Int Workshop Tools Artif Intell Archit Lang Algorithms

Other

OtherIEEE International Workshop on Tools for Artificial Intelligence: Architectures, Languages and Algorithms
CityFairfax, VA, USA
Period10/23/8910/25/89

ASJC Scopus subject areas

  • Engineering(all)

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