Packaging of GaAs Signal Processors on Multichip Modules

Deposited multichip modules (MCM-D's) are in their infancy for use with conventional CMOS-based digital computing systems operating at 100-MHz clock rates, and even more immature from the perspective of high clock rate silicon ECL and GaAs-based processors operating at hundreds of megahertz or low gigahertz clock rates. In this paper, we discuss the extensions to the MCM-D fabrication technology, and to the design and layout of these structures, which will have to be made to accommodate high clock rate ECL and GaAs digital integrated circuits. Techniques for attachment of the high clock rate chips to the MCM-D's will be discussed, including wire bond, tape automated bond (TAB), flip-chip solder attachment, and flip adhesives; the trade-offs between these different approaches will be noted. Electrical issues which must be addressed include minimizing signal amplitude losses in the small cross section interconnects typical of MCM-D's, minimization of interline cross talk through proper layout and design rules, provision of integral thin film termination resistors of excellent electrical quality, and the provision of integral decoupling capacitors to suppress inductively generated noise on the power and ground planes. The problem of launching fast rise time, wide bandwidth signals onto and retrieving such signals from the MCM–D's will be noted. The thermal problems associated with the packing of 10–50 high power dissipation chips onto such small structures will be discussed, along with methods of removing such high levels of heat by changes in materials incorporated into the stacked structures. Finally, several MCM-D design and fabrication projects under way at the Mayo Foundation in collaboration with corporate partners which attempt to address and solve some of the problems cited above will be described, along with some of the initial results of these studies.