Overcoming the challenges of crossbar resistive memory architectures

Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie

Research output: Chapter in Book/Report/Conference proceedingConference contribution

140 Scopus citations

Abstract

The scalability of DRAM faces challenges from increasing power consumption and the difficulty of building high aspect ratio capacitors. Consequently, emerging memory technologies including Phase Change Memory (PCM), Spin-Transfer Torque RAM (STT-RAM), and Resistive RAM (ReRAM) are being actively pursued as replacements for DRAM memory. Among these candidates, ReRAM has superior characteristics such as high density, low write energy, and high endurance, making it a very attractive cost-efficient alternative to DRAM. In this paper, we present a comprehensive study of ReRAM-based memory systems. ReRAM's high density comes from its unique crossbar architecture where some peripheral circuits are laid below multiple layers of ReRAM cells. A crossbar architecture introduces special constraints on operating voltages, write latency, and array size. The access latency of a crossbar is a function of the data patterns involved in a write operation. These combined with ReRAM's exponential relationship between its write voltage and switching latency provide opportunities for architectural optimizations. This paper makes several key contributions. First, we study the crossbar architecture and describe trade-offs involving voltage drop, write latency, and data pattern. We then analyze microarchitectural enhancements such as double-sided ground biasing and multiphase reset operations to improve write performance. At the architecture level, a simple compression based data encoding scheme is proposed to further bring down the latency. As the compressibility of a block varies based on its content, write latency is not uniform across blocks. To mitigate the impact of slow writes on performance, we propose and evaluate a novel scheduling policy that makes writing decisions based on latency and activity of a bank. The experimental results show that our architecture improves the performance of a system using ReRAM-based main memory by about 44% over a conservative baseline and 14% over an aggressive baseline on average, and has less than 10% performance degradation compared to an ideal DRAM-only system.

Original languageEnglish (US)
Title of host publication2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages476-488
Number of pages13
ISBN (Electronic)9781479989300
DOIs
StatePublished - Mar 6 2015
Event2015 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015 - Burlingame, United States
Duration: Feb 7 2015Feb 11 2015

Publication series

Name2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015

Other

Other2015 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015
CountryUnited States
CityBurlingame
Period2/7/152/11/15

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ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Software

Cite this

Xu, C., Niu, D., Muralimanohar, N., Balasubramonian, R., Zhang, T., Yu, S., & Xie, Y. (2015). Overcoming the challenges of crossbar resistive memory architectures. In 2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015 (pp. 476-488). [7056056] (2015 IEEE 21st International Symposium on High Performance Computer Architecture, HPCA 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HPCA.2015.7056056