Out-of-order issue logic using sorting networks

Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A fundamental property of superscalar architectures is the execution of multiple instructions per cycle. To accomplish this, the issue logic selects and prioritizes the instructions whose operands will be ready in the next cycle, using wakeup, select and queue update logic. By incorporating the issue logic in one pipeline stage, dependent instructions can be issued in consecutive cycles. However, the many serial operations required makes this problematic from a circuit delay perspective. In this paper, we propose an issue queue design that divides the ready signals into groups, sorts the groups in parallel and provides four oldest ready instructions for issue, with single-cycle operation. Static CMOS select and update logic reduces power and low fan-out in many stages improves circuit speed. The complete issue logic requires 30 inversions, allowing simulated circuit operation at over 3 GHz in a foundry 45nm SOI fabrication process.

Original languageEnglish (US)
Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Pages385-388
Number of pages4
DOIs
StatePublished - 2010
Event20th Great Lakes Symposium on VLSI, GLSVLSI 2010 - Providence, RI, United States
Duration: May 16 2010May 18 2010

Other

Other20th Great Lakes Symposium on VLSI, GLSVLSI 2010
CountryUnited States
CityProvidence, RI
Period5/16/105/18/10

Fingerprint

Sorting
Delay circuits
Networks (circuits)
Foundries
Fans
Pipelines
Fabrication

Keywords

  • high speed circuits
  • ILP
  • issue queue
  • micro-architecture
  • out-of-order processing

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Mhambrey, S. S., Clark, L. T., Maurya, S. K., & Berezowski, K. S. (2010). Out-of-order issue logic using sorting networks. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (pp. 385-388) https://doi.org/10.1145/1785481.1785570

Out-of-order issue logic using sorting networks. / Mhambrey, Siddhesh S.; Clark, Lawrence T.; Maurya, Satendra Kumar; Berezowski, Krzysztof S.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2010. p. 385-388.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mhambrey, SS, Clark, LT, Maurya, SK & Berezowski, KS 2010, Out-of-order issue logic using sorting networks. in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. pp. 385-388, 20th Great Lakes Symposium on VLSI, GLSVLSI 2010, Providence, RI, United States, 5/16/10. https://doi.org/10.1145/1785481.1785570
Mhambrey SS, Clark LT, Maurya SK, Berezowski KS. Out-of-order issue logic using sorting networks. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2010. p. 385-388 https://doi.org/10.1145/1785481.1785570
Mhambrey, Siddhesh S. ; Clark, Lawrence T. ; Maurya, Satendra Kumar ; Berezowski, Krzysztof S. / Out-of-order issue logic using sorting networks. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2010. pp. 385-388
@inproceedings{21968199b9e54b4396a6f36e2e5e7771,
title = "Out-of-order issue logic using sorting networks",
abstract = "A fundamental property of superscalar architectures is the execution of multiple instructions per cycle. To accomplish this, the issue logic selects and prioritizes the instructions whose operands will be ready in the next cycle, using wakeup, select and queue update logic. By incorporating the issue logic in one pipeline stage, dependent instructions can be issued in consecutive cycles. However, the many serial operations required makes this problematic from a circuit delay perspective. In this paper, we propose an issue queue design that divides the ready signals into groups, sorts the groups in parallel and provides four oldest ready instructions for issue, with single-cycle operation. Static CMOS select and update logic reduces power and low fan-out in many stages improves circuit speed. The complete issue logic requires 30 inversions, allowing simulated circuit operation at over 3 GHz in a foundry 45nm SOI fabrication process.",
keywords = "high speed circuits, ILP, issue queue, micro-architecture, out-of-order processing",
author = "Mhambrey, {Siddhesh S.} and Clark, {Lawrence T.} and Maurya, {Satendra Kumar} and Berezowski, {Krzysztof S.}",
year = "2010",
doi = "10.1145/1785481.1785570",
language = "English (US)",
isbn = "9781450300124",
pages = "385--388",
booktitle = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

}

TY - GEN

T1 - Out-of-order issue logic using sorting networks

AU - Mhambrey, Siddhesh S.

AU - Clark, Lawrence T.

AU - Maurya, Satendra Kumar

AU - Berezowski, Krzysztof S.

PY - 2010

Y1 - 2010

N2 - A fundamental property of superscalar architectures is the execution of multiple instructions per cycle. To accomplish this, the issue logic selects and prioritizes the instructions whose operands will be ready in the next cycle, using wakeup, select and queue update logic. By incorporating the issue logic in one pipeline stage, dependent instructions can be issued in consecutive cycles. However, the many serial operations required makes this problematic from a circuit delay perspective. In this paper, we propose an issue queue design that divides the ready signals into groups, sorts the groups in parallel and provides four oldest ready instructions for issue, with single-cycle operation. Static CMOS select and update logic reduces power and low fan-out in many stages improves circuit speed. The complete issue logic requires 30 inversions, allowing simulated circuit operation at over 3 GHz in a foundry 45nm SOI fabrication process.

AB - A fundamental property of superscalar architectures is the execution of multiple instructions per cycle. To accomplish this, the issue logic selects and prioritizes the instructions whose operands will be ready in the next cycle, using wakeup, select and queue update logic. By incorporating the issue logic in one pipeline stage, dependent instructions can be issued in consecutive cycles. However, the many serial operations required makes this problematic from a circuit delay perspective. In this paper, we propose an issue queue design that divides the ready signals into groups, sorts the groups in parallel and provides four oldest ready instructions for issue, with single-cycle operation. Static CMOS select and update logic reduces power and low fan-out in many stages improves circuit speed. The complete issue logic requires 30 inversions, allowing simulated circuit operation at over 3 GHz in a foundry 45nm SOI fabrication process.

KW - high speed circuits

KW - ILP

KW - issue queue

KW - micro-architecture

KW - out-of-order processing

UR - http://www.scopus.com/inward/record.url?scp=77954464992&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77954464992&partnerID=8YFLogxK

U2 - 10.1145/1785481.1785570

DO - 10.1145/1785481.1785570

M3 - Conference contribution

SN - 9781450300124

SP - 385

EP - 388

BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

ER -