OTA-Free 1-1 MASH ADC Using Fully Passive Noise-Shaping SAR VCO ADC

Sanjeev Tannirkulam Chandrasekaran, Sumukh Prashant Bhanushali, Stefano Pietri, Arindam Sanyal

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


We present an OTA-free 1-1 multi-stage noise-shaping (MASH) analog-to-digital converter (ADC) utilizing a fully passive noise-shaping successive approximation register (NS-SAR) as the first stage and an open-loop ring voltage-controlled oscillator (VCO) as the second stage. The key contribution of this work is to address the challenge of driving large sampling capacitors for high-resolution NS-SAR. The proposed architecture allows a low-resolution NS-SAR stage and leverages residue attenuation due to passive charge sharing in the NS-SAR to linearize the VCO. The MASH architecture suppresses quantization noise and SAR comparator noise at the ADC output, and the high pass shapes VCO thermal noise. In addition, we demonstrate a computationally inexpensive foreground inter-stage gain calibration algorithm for the proposed ADC architecture. The prototype ADC consumes 0.16 mW while achieving an SNDR/DR of 71.5/75.8 dB over a 1.1-MHz bandwidth and Walden FoM of 23.3 fJ/step, which is the lowest in 65-nm technology.

Original languageEnglish (US)
Pages (from-to)1100-1111
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Issue number4
StatePublished - Apr 1 2022


  • Multi-stage noise-shaping (MASH)
  • noise-shaping successive approximation register
  • oversampling analog-to-digital converter (ADC)
  • passive integrator
  • ring voltage-controlled oscillator (VCO)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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