TY - GEN
T1 - OTA-free 1-1 MASH ADC using Fully Passive Noise Shaping SAR VCO ADC
AU - Chandrasekaran, Sanjeev Tannirkulam
AU - Bhanushali, Sumukh P.
AU - Pietri, Stefano
AU - Sanyal, Arindam
N1 - Publisher Copyright:
© 2021 JSAP.
PY - 2021/6/13
Y1 - 2021/6/13
N2 - We present an OTA-free 1-1 MASH ADC utilizing a fully passive noise shaping (FPNS) SAR as first-stage and open-loop VCO ADC as second stage. The key contribution of this work is to address the challenge of driving large sampling capacitor for high resolution NS-SAR. The proposed architecture reduces resolution of SAR stage and leverages residue attenuation due to passive charge sharing in the FPNS SAR to linearize the VCO. Combining an FPNS SAR with a VCO ADC shapes in-band thermal noise of VCO and SAR comparator at ADC output. Additionally, we demonstrate a computationally inexpensive foreground inter-stage gain calibration algorithm for the proposed ADC architecture. The prototype ADC consumes 0.16mW while achieving an SNDR/DR of 71.5/75.8dB over a 1.1MHz bandwidth and walden FoM of 23.3fJ/step which is the lowest in 65nm technology.
AB - We present an OTA-free 1-1 MASH ADC utilizing a fully passive noise shaping (FPNS) SAR as first-stage and open-loop VCO ADC as second stage. The key contribution of this work is to address the challenge of driving large sampling capacitor for high resolution NS-SAR. The proposed architecture reduces resolution of SAR stage and leverages residue attenuation due to passive charge sharing in the FPNS SAR to linearize the VCO. Combining an FPNS SAR with a VCO ADC shapes in-band thermal noise of VCO and SAR comparator at ADC output. Additionally, we demonstrate a computationally inexpensive foreground inter-stage gain calibration algorithm for the proposed ADC architecture. The prototype ADC consumes 0.16mW while achieving an SNDR/DR of 71.5/75.8dB over a 1.1MHz bandwidth and walden FoM of 23.3fJ/step which is the lowest in 65nm technology.
KW - inter-stage gain calibration and MASH
KW - noise-shaping SAR
KW - oversampling ADC
KW - ring VCO
UR - http://www.scopus.com/inward/record.url?scp=85111850926&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85111850926&partnerID=8YFLogxK
U2 - 10.23919/VLSICircuits52068.2021.9492344
DO - 10.23919/VLSICircuits52068.2021.9492344
M3 - Conference contribution
AN - SCOPUS:85111850926
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
BT - 2021 Symposium on VLSI Circuits, VLSI Circuits 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Symposium on VLSI Circuits, VLSI Circuits 2021
Y2 - 13 June 2021 through 19 June 2021
ER -