Abstract

Resistive RAM (ReRAM) has fast access time, ultra-low stand-by power and high reliability, making it a viable memory technology to replace DRAM for main memory. The 1-Transistor-1-resistor (1T1R) ReRAM array has density comparable to that of a DRAM array and the advantages of lower programming energy and higher reliability compared to the ultrahigh density ReRAM cross-point array. In this paper, we show how circuit operation parameters, such as the pulse amplitude and pulse widths of word-line (WL) voltage, bit-line (BL) voltage, and source-line (SL) voltage can be used to lower latency, lower power and improve reliability. SPICE simulation results demonstrate that appropriate choice of voltage settings can be used to reduce the write latency of the 1T1R cell by 29.4% and reduce write energy by 46.7% over the DRAM cell. Next, we show how the endurance of ReRAM cell can be improved by increasing the ratio between OFF and ON resistances and reducing SL voltage. We find that of these, reducing the SL voltage results in significant improvement in endurance with smaller energy overhead. Next, we evaluate the system-level performance of a 1GB ReRAM and DRAM memory system using CACTI and GEM5. Simulation results using SPEC CPU INT 2006 and DaCapo-9.12 benchmarks show that the ReRAM based main memory can improve IPC by 4.2% and energy by up to 77.8% compared to a DRAM system.

Original languageEnglish (US)
Title of host publicationProceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages359-366
Number of pages8
ISBN (Print)9781467371650
DOIs
StatePublished - Dec 14 2015
Event33rd IEEE International Conference on Computer Design, ICCD 2015 - New York City, United States
Duration: Oct 18 2015Oct 21 2015

Other

Other33rd IEEE International Conference on Computer Design, ICCD 2015
CountryUnited States
CityNew York City
Period10/18/1510/21/15

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Keywords

  • 1T1R ReRAM
  • energy
  • IPC
  • latency
  • main memory
  • reliability

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications

Cite this

Mao, M., Cao, Y., Yu, S., & Chakrabarti, C. (2015). Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings. In Proceedings of the 33rd IEEE International Conference on Computer Design, ICCD 2015 (pp. 359-366). [7357125] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCD.2015.7357125