TY - GEN
T1 - Optimized circuit failure prediction for aging
T2 - International Test Conference 2008, ITC 2008
AU - Agarwal, Mridul
AU - Balakrishnan, Varsha
AU - Bhuyan, Anshuman
AU - Kim, Kyunglok
AU - Paul, Bipul C.
AU - Wang, Wenping
AU - Yang, Bo
AU - Cao, Yu
AU - Mitra, Subhasish
N1 - Copyright:
Copyright 2013 Elsevier B.V., All rights reserved.
PY - 2008
Y1 - 2008
N2 - Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias- Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such aging mechanisms. Circuit failure prediction uses special on-chip circuits called aging sensors. In this paper, we experimentally demonstrate correct functionality and practicality of two flavors of flip-flop designs with built-in aging sensors using 90nm test chips. We also present an aging-aware timing analysis technique to strategically place such flip-flops with built-in aging sensors at selective locations inside a chip for effective circuit failure prediction. This aging-aware timing analysis approach also minimizes the chip-level area impact of such aging sensors. Results from two 90nm designs demonstrate the practicality and effectiveness of optimized circuit failure prediction with overall chip-level area impact of 2.5% and 0.6%.
AB - Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias- Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such aging mechanisms. Circuit failure prediction uses special on-chip circuits called aging sensors. In this paper, we experimentally demonstrate correct functionality and practicality of two flavors of flip-flop designs with built-in aging sensors using 90nm test chips. We also present an aging-aware timing analysis technique to strategically place such flip-flops with built-in aging sensors at selective locations inside a chip for effective circuit failure prediction. This aging-aware timing analysis approach also minimizes the chip-level area impact of such aging sensors. Results from two 90nm designs demonstrate the practicality and effectiveness of optimized circuit failure prediction with overall chip-level area impact of 2.5% and 0.6%.
UR - http://www.scopus.com/inward/record.url?scp=67249159156&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67249159156&partnerID=8YFLogxK
U2 - 10.1109/TEST.2008.4700619
DO - 10.1109/TEST.2008.4700619
M3 - Conference contribution
AN - SCOPUS:67249159156
SN - 9781424424030
T3 - Proceedings - International Test Conference
BT - Proceedings - International Test Conference 2008, ITC 2008
Y2 - 28 October 2008 through 30 October 2008
ER -