Optimized circuit failure prediction for aging

Practicality and promise

Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra

Research output: Chapter in Book/Report/Conference proceedingConference contribution

103 Citations (Scopus)

Abstract

Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias- Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such aging mechanisms. Circuit failure prediction uses special on-chip circuits called aging sensors. In this paper, we experimentally demonstrate correct functionality and practicality of two flavors of flip-flop designs with built-in aging sensors using 90nm test chips. We also present an aging-aware timing analysis technique to strategically place such flip-flops with built-in aging sensors at selective locations inside a chip for effective circuit failure prediction. This aging-aware timing analysis approach also minimizes the chip-level area impact of such aging sensors. Results from two 90nm designs demonstrate the practicality and effectiveness of optimized circuit failure prediction with overall chip-level area impact of 2.5% and 0.6%.

Original languageEnglish (US)
Title of host publicationProceedings - International Test Conference
DOIs
StatePublished - 2008
EventInternational Test Conference 2008, ITC 2008 - Santa Clara, CA, United States
Duration: Oct 28 2008Oct 30 2008

Other

OtherInternational Test Conference 2008, ITC 2008
CountryUnited States
CitySanta Clara, CA
Period10/28/0810/30/08

Fingerprint

Aging of materials
Networks (circuits)
Prediction
Chip
Timing Analysis
Sensor
Flip flop circuits
Sensors
Flip
Flavors
Demonstrate
Degradation
Minimise
Predict

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Agarwal, M., Balakrishnan, V., Bhuyan, A., Kim, K., Paul, B. C., Wang, W., ... Mitra, S. (2008). Optimized circuit failure prediction for aging: Practicality and promise. In Proceedings - International Test Conference [4700619] https://doi.org/10.1109/TEST.2008.4700619

Optimized circuit failure prediction for aging : Practicality and promise. / Agarwal, Mridul; Balakrishnan, Varsha; Bhuyan, Anshuman; Kim, Kyunglok; Paul, Bipul C.; Wang, Wenping; Yang, Bo; Cao, Yu; Mitra, Subhasish.

Proceedings - International Test Conference. 2008. 4700619.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Agarwal, M, Balakrishnan, V, Bhuyan, A, Kim, K, Paul, BC, Wang, W, Yang, B, Cao, Y & Mitra, S 2008, Optimized circuit failure prediction for aging: Practicality and promise. in Proceedings - International Test Conference., 4700619, International Test Conference 2008, ITC 2008, Santa Clara, CA, United States, 10/28/08. https://doi.org/10.1109/TEST.2008.4700619
Agarwal M, Balakrishnan V, Bhuyan A, Kim K, Paul BC, Wang W et al. Optimized circuit failure prediction for aging: Practicality and promise. In Proceedings - International Test Conference. 2008. 4700619 https://doi.org/10.1109/TEST.2008.4700619
Agarwal, Mridul ; Balakrishnan, Varsha ; Bhuyan, Anshuman ; Kim, Kyunglok ; Paul, Bipul C. ; Wang, Wenping ; Yang, Bo ; Cao, Yu ; Mitra, Subhasish. / Optimized circuit failure prediction for aging : Practicality and promise. Proceedings - International Test Conference. 2008.
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