Abstract
Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias- Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such aging mechanisms. Circuit failure prediction uses special on-chip circuits called aging sensors. In this paper, we experimentally demonstrate correct functionality and practicality of two flavors of flip-flop designs with built-in aging sensors using 90nm test chips. We also present an aging-aware timing analysis technique to strategically place such flip-flops with built-in aging sensors at selective locations inside a chip for effective circuit failure prediction. This aging-aware timing analysis approach also minimizes the chip-level area impact of such aging sensors. Results from two 90nm designs demonstrate the practicality and effectiveness of optimized circuit failure prediction with overall chip-level area impact of 2.5% and 0.6%.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - International Test Conference |
| DOIs | |
| State | Published - 2008 |
| Event | International Test Conference 2008, ITC 2008 - Santa Clara, CA, United States Duration: Oct 28 2008 → Oct 30 2008 |
Other
| Other | International Test Conference 2008, ITC 2008 |
|---|---|
| Country | United States |
| City | Santa Clara, CA |
| Period | 10/28/08 → 10/30/08 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Applied Mathematics
Cite this
Optimized circuit failure prediction for aging : Practicality and promise. / Agarwal, Mridul; Balakrishnan, Varsha; Bhuyan, Anshuman; Kim, Kyunglok; Paul, Bipul C.; Wang, Wenping; Yang, Bo; Cao, Yu; Mitra, Subhasish.
Proceedings - International Test Conference. 2008. 4700619.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Optimized circuit failure prediction for aging
T2 - Practicality and promise
AU - Agarwal, Mridul
AU - Balakrishnan, Varsha
AU - Bhuyan, Anshuman
AU - Kim, Kyunglok
AU - Paul, Bipul C.
AU - Wang, Wenping
AU - Yang, Bo
AU - Cao, Yu
AU - Mitra, Subhasish
PY - 2008
Y1 - 2008
N2 - Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias- Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such aging mechanisms. Circuit failure prediction uses special on-chip circuits called aging sensors. In this paper, we experimentally demonstrate correct functionality and practicality of two flavors of flip-flop designs with built-in aging sensors using 90nm test chips. We also present an aging-aware timing analysis technique to strategically place such flip-flops with built-in aging sensors at selective locations inside a chip for effective circuit failure prediction. This aging-aware timing analysis approach also minimizes the chip-level area impact of such aging sensors. Results from two 90nm designs demonstrate the practicality and effectiveness of optimized circuit failure prediction with overall chip-level area impact of 2.5% and 0.6%.
AB - Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias- Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such aging mechanisms. Circuit failure prediction uses special on-chip circuits called aging sensors. In this paper, we experimentally demonstrate correct functionality and practicality of two flavors of flip-flop designs with built-in aging sensors using 90nm test chips. We also present an aging-aware timing analysis technique to strategically place such flip-flops with built-in aging sensors at selective locations inside a chip for effective circuit failure prediction. This aging-aware timing analysis approach also minimizes the chip-level area impact of such aging sensors. Results from two 90nm designs demonstrate the practicality and effectiveness of optimized circuit failure prediction with overall chip-level area impact of 2.5% and 0.6%.
UR - http://www.scopus.com/inward/record.url?scp=67249159156&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67249159156&partnerID=8YFLogxK
U2 - 10.1109/TEST.2008.4700619
DO - 10.1109/TEST.2008.4700619
M3 - Conference contribution
SN - 9781424424030
BT - Proceedings - International Test Conference
ER -