Optimization of multi-channel BCH error decoding for common cases

Russ Dill, Aviral Shrivastava, Hyunok Oh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. We break the BCH decoding process into its three basic blocks: syndrome calculation, the error locator polynomial generation, and the roots of the error locator polynomial computation. While an existing multi-channel BCH decoder consists of several single-channel BCH decoders operating in parallel, this paper utilizes a pooled group of shared decoding blocks. By considering the frequency of errors, the proposed pooled group approach requires fewer hardware blocks than in a traditional multi-channel configuration with a negligible impact on performance. Combined with a specialized root finding unit for blocks with only 1 error, our scheme reduces hardware area by 47%-71% and dynamic power by 44%-59% with 2% performance degradation in typical NAND flash systems. With a constant hardware area, the proposed scheme can improve throughput by 3x-5x or NAND flash lifetime by 1.4x-4.5x.

Original languageEnglish (US)
Title of host publication2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages59-68
Number of pages10
ISBN (Print)9781467383202
DOIs
StatePublished - Nov 10 2015
EventInternational Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015 - Amsterdam, Netherlands
Duration: Oct 4 2015Oct 9 2015

Other

OtherInternational Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015
CountryNetherlands
CityAmsterdam
Period10/4/1510/9/15

Keywords

  • Clocks
  • Error correction codes
  • Force
  • Polynomials
  • Throughput

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Science Applications

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  • Cite this

    Dill, R., Shrivastava, A., & Oh, H. (2015). Optimization of multi-channel BCH error decoding for common cases. In 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015 (pp. 59-68). [7324546] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CASES.2015.7324546