TY - GEN
T1 - Optimization of multi-channel BCH error decoding for common cases
AU - Dill, Russ
AU - Shrivastava, Aviral
AU - Oh, Hyunok
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/11/10
Y1 - 2015/11/10
N2 - This paper proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. We break the BCH decoding process into its three basic blocks: syndrome calculation, the error locator polynomial generation, and the roots of the error locator polynomial computation. While an existing multi-channel BCH decoder consists of several single-channel BCH decoders operating in parallel, this paper utilizes a pooled group of shared decoding blocks. By considering the frequency of errors, the proposed pooled group approach requires fewer hardware blocks than in a traditional multi-channel configuration with a negligible impact on performance. Combined with a specialized root finding unit for blocks with only 1 error, our scheme reduces hardware area by 47%-71% and dynamic power by 44%-59% with 2% performance degradation in typical NAND flash systems. With a constant hardware area, the proposed scheme can improve throughput by 3x-5x or NAND flash lifetime by 1.4x-4.5x.
AB - This paper proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. We break the BCH decoding process into its three basic blocks: syndrome calculation, the error locator polynomial generation, and the roots of the error locator polynomial computation. While an existing multi-channel BCH decoder consists of several single-channel BCH decoders operating in parallel, this paper utilizes a pooled group of shared decoding blocks. By considering the frequency of errors, the proposed pooled group approach requires fewer hardware blocks than in a traditional multi-channel configuration with a negligible impact on performance. Combined with a specialized root finding unit for blocks with only 1 error, our scheme reduces hardware area by 47%-71% and dynamic power by 44%-59% with 2% performance degradation in typical NAND flash systems. With a constant hardware area, the proposed scheme can improve throughput by 3x-5x or NAND flash lifetime by 1.4x-4.5x.
KW - Clocks
KW - Error correction codes
KW - Force
KW - Polynomials
KW - Throughput
UR - http://www.scopus.com/inward/record.url?scp=84962216143&partnerID=8YFLogxK
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U2 - 10.1109/CASES.2015.7324546
DO - 10.1109/CASES.2015.7324546
M3 - Conference contribution
AN - SCOPUS:84962216143
T3 - 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015
SP - 59
EP - 68
BT - 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015
Y2 - 4 October 2015 through 9 October 2015
ER -