Optimal scheduling of signature analysis for VLSI testing

Y. H. Lee, C. M. Krishna

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

A simple algorithm is presented which minimizes the mean testing time for VLSI circuits. By breaking up the testing process into subintervals, and analyzing the signature at the end of each subinterval, it is possible to abort future tests if the circuit is found to be faulty, thus saving test time. Subdivision of the test process also reduces the probability of aliasing, thus increasing the effective coverage of the signature analysis process. Also, if the process is sufficiently subdivided, it may be possible to use the test results not only to determine if the circuit is faulty or not, but to diagnose the fault.

Original languageEnglish (US)
Title of host publicationDigest of Papers - International Test Conference
PublisherPubl by IEEE
Pages443-451
Number of pages9
ISBN (Print)0818608706
StatePublished - Dec 1 1988
Externally publishedYes

Publication series

NameDigest of Papers - International Test Conference
ISSN (Print)0743-1686

ASJC Scopus subject areas

  • Engineering(all)

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