Optimal layout of hexagonal minimum spanning trees in linear time

Guo Hui Lin, Guoliang Xue

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

With the advent of deep sub-micron technology, gate delays are much smaller than wire delays. As a result, hexagonal Steiner minimum trees have received extensive study recently because of their applications in VLSI physical design. Just like its rectilinear and Euclidean counterparts, the hexagonal Steiner minimum tree problem can be shown to be NP-hard. Therefore polynomial time approximation algorithms are of great interest. In a recent paper, Lin, Xue and Zhou proposed a quadratic time algorithm to compute an optimal layout of a hexagonal minimum spanning tree with attractive computational results. In this paper, we present an improved linear time algorithm for computing an optimal layout of a hexagonal minimum spanning tree.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
Volume4
StatePublished - 2000
Externally publishedYes
EventProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz
Duration: May 28 2000May 31 2000

Other

OtherProceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems
CityGeneva, Switz
Period5/28/005/31/00

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Lin, G. H., & Xue, G. (2000). Optimal layout of hexagonal minimum spanning trees in linear time. In Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 4). IEEE.