Abstract
With the advent of deep sub-micron technology, gate delays are much smaller than wire delays. As a result, hexagonal Steiner minimum trees have received extensive study recently because of their applications in VLSI physical design. Just like its rectilinear and Euclidean counterparts, the hexagonal Steiner minimum tree problem can be shown to be NP-hard. Therefore polynomial time approximation algorithms are of great interest. In a recent paper, Lin, Xue and Zhou proposed a quadratic time algorithm to compute an optimal layout of a hexagonal minimum spanning tree with attractive computational results. In this paper, we present an improved linear time algorithm for computing an optimal layout of a hexagonal minimum spanning tree.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
Publisher | IEEE |
Volume | 4 |
State | Published - 2000 |
Externally published | Yes |
Event | Proceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems - Geneva, Switz Duration: May 28 2000 → May 31 2000 |
Other
Other | Proceedings of the IEEE 2000 Internaitonal Symposium on Circuits and Systems |
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City | Geneva, Switz |
Period | 5/28/00 → 5/31/00 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials