Abstract
An important aspect of hardware-software co-design is partitioning of task to be scheduled on the hardware and software resources. Existing approaches separate partitioning and scheduling in two steps. Since partitioning solutions affect scheduling results and vice versa, the existing sequential approaches may lead to sub-optimal results. In this paper, we present an integrated hardware/software scheduling, partitioning and binding strategy. We use dynamic programming techniques to devise an optimal solution for partitioning of a given concurrent task graph, which models the co-design problem, for execution on one software (single CPU) and several hardware resources (multiple FPGA's), with the objective of minimizing the total execution time. Our implementation shows that we can solve problem instances where the task graph has 40 nodes and 600 edges in less than a second.
| Original language | English (US) |
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| Title of host publication | Proceedings of the IEEE International Conference on VLSI Design |
| Place of Publication | Los Alamitos, CA, United States |
| Publisher | IEEE |
| Pages | 110-113 |
| Number of pages | 4 |
| State | Published - 2000 |
| Externally published | Yes |
| Event | The 13th International Conference on VLSI Design: Wireless and Digital Imaging in the Millennium - Calcutta, India Duration: Jan 3 2000 → Jan 7 2000 |
Other
| Other | The 13th International Conference on VLSI Design: Wireless and Digital Imaging in the Millennium |
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| City | Calcutta, India |
| Period | 1/3/00 → 1/7/00 |
ASJC Scopus subject areas
- General Engineering