Optimal design of master-worker architecture for parallelized simulation optimization

Haobin Li, Xiuju Fu, Xiao Feng Yin, Giulia Pedrielli, Loo Hay Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This study formulates and solves the design problem for a master-worker architecture dedicated to the implementation of a parallelized simulation optimization algorithm. Such a formulation does not assume any specific characteristic of the optimization problem being solved, but the way the algorithm is parallelized. In particular, we refer to the master-worker paradigm, where the master makes sampling decisions while the workers receive solutions to evaluate. We identify two metrics to be optimized: the throughput of the workers in terms of the number of evaluations per time unit, and the lack of synchronization between the master and the workers. We identify several design parameters: number of workers (n), the buffer size for each worker and for the master and the sample size m, i.e., the number of solutions used by the master for sampling decisions at each iteration. Numerical experiments show optimal designs over randomly generated simulation optimization algorithm instances.

Original languageEnglish (US)
Title of host publication2017 Winter Simulation Conference, WSC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2183-2193
Number of pages11
ISBN (Electronic)9781538634288
DOIs
StatePublished - Jan 4 2018
Event2017 Winter Simulation Conference, WSC 2017 - Las Vegas, United States
Duration: Dec 3 2017Dec 6 2017

Other

Other2017 Winter Simulation Conference, WSC 2017
CountryUnited States
CityLas Vegas
Period12/3/1712/6/17

ASJC Scopus subject areas

  • Software
  • Modeling and Simulation
  • Computer Science Applications

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  • Cite this

    Li, H., Fu, X., Yin, X. F., Pedrielli, G., & Lee, L. H. (2018). Optimal design of master-worker architecture for parallelized simulation optimization. In 2017 Winter Simulation Conference, WSC 2017 (pp. 2183-2193). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/WSC.2017.8247950