TY - JOUR
T1 - Optimal Design and Sequential Analysis of VLSI Testing Strategy
AU - Yu, Philip S.
AU - Lee, Yann Hang
N1 - Funding Information:
Manuscript received January 28, 1986; revised January 28, 1987. This work was supported in part by the National Science Foundation under Grant NSFDMC-8504971 to C. M. Krishna. P. S. Yu and Y.-H. Lee are with IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10598. C. M. Krishna is with the Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003. IEEE Log Number 8716363.
PY - 1988/3
Y1 - 1988/3
N2 - In this paper, we present a new method for determining the optimal testing period and measuring the production yield. With the increased complexity of VLSI circuits, testing has become more costly and time consuming. The design of a testing strategy, which is specified by the testing period based on the coverage function of the testing algorithm, involves trading off of the cost of testing and the penalty of passing a bad chip as good. We first derive the optimal testing period assuming the production yield is known. Since the yield may not be known a priori, we next develop an optimal sequential testing strategy which estimates the yield based on ongoing testing results, which in turn determines the optimal testing period. Finally, we present the optimal sequential testing strategy for batches in which N chips are tested simultaneously. The results will be of use whether the yield stays constant or varies from one manufacturing run to another.
AB - In this paper, we present a new method for determining the optimal testing period and measuring the production yield. With the increased complexity of VLSI circuits, testing has become more costly and time consuming. The design of a testing strategy, which is specified by the testing period based on the coverage function of the testing algorithm, involves trading off of the cost of testing and the penalty of passing a bad chip as good. We first derive the optimal testing period assuming the production yield is known. Since the yield may not be known a priori, we next develop an optimal sequential testing strategy which estimates the yield based on ongoing testing results, which in turn determines the optimal testing period. Finally, we present the optimal sequential testing strategy for batches in which N chips are tested simultaneously. The results will be of use whether the yield stays constant or varies from one manufacturing run to another.
KW - Consistent estimation
KW - VLSI testing strategy
KW - design of experiments
KW - performance analysis
KW - sequential decision
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U2 - 10.1109/12.2171
DO - 10.1109/12.2171
M3 - Article
AN - SCOPUS:0023961362
VL - 37
SP - 339
EP - 347
JO - IEEE Transactions on Computers
JF - IEEE Transactions on Computers
SN - 0018-9340
IS - 3
ER -