Operation tables for scheduling in the presence of incomplete bypassing

Aviral Shrivastava, Eugene Earlie, Nikil Dutt, Alex Nicolaut

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing has significant impact on cycle time, area, and power consumption of the processor. Due to the strict constraints on performance, cost and power consumption in embedded processors, architects need to evaluate and implement incomplete register bypassing mechanisms. However traditional data hazard detection and/or avoidance techniques used in retargetable schedulers break down in the presence of incomplete bypassing. In this paper, we present the concept of Operation Tables, which can be used to detect data hazards, even in the presence of incomplete bypassing. Further-more our technique integrates the detection of both data, as well as resource hazards, and can be easily employed in a compiler to generate better schedules. Our experimental results on the popular Intel XScale embedded processor platform show that even with a simple intra-basic block scheduling technique, we achieve upto 20% performance improvement over fully optimized GCC generated code on embedded applications from the MiBench suite.

Original languageEnglish (US)
Title of host publicationInternational Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004
Pages194-199
Number of pages6
StatePublished - Dec 1 2004
Externally publishedYes
EventSecond IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004 - Stockholm, Sweden
Duration: Sep 8 2004Sep 10 2004

Publication series

NameSecond IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, CODES+ISSS 2004

Other

OtherSecond IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004
CountrySweden
CityStockholm
Period9/8/049/10/04

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Keywords

  • Bypass
  • Hazard Detection
  • Operation Table
  • Reservation Table
  • Retargetable Compilers
  • Scheduling

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Shrivastava, A., Earlie, E., Dutt, N., & Nicolaut, A. (2004). Operation tables for scheduling in the presence of incomplete bypassing. In International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004 (pp. 194-199). (Second IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis, CODES+ISSS 2004).