On the structure of the recessed-channel MOSFET for sub-100 nm Si CMOS

A theoretical study is presented to understand misalignment tolerance and process window for channel depth in the recessed-channel MOSFET for sub-100 nm Si CMOS. Simulations of the device at 100 nm demonstrate that the device is misalignment tolerant if it possesses two features: (1) symmetric source/drain (S/D) doping profiles and (2) a T-shaped gate. In addition, a relatively positive S/D junction depth with respect to the recessed channel provides a process window for channel depth. Therefore, a new device structure is proposed for the recessed-channel MOSFET, T-gate recessed-channel MOSFET, which can be fabricated with standard Si CMOS processes.