On the structure of the recessed-channel MOSFET for sub-100 nm Si CMOS

Meng Tao, Kody Varahramyan

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A theoretical study is presented to understand misalignment tolerance and process window for channel depth in the recessed-channel MOSFET for sub-100 nm Si CMOS. Simulations of the device at 100 nm demonstrate that the device is misalignment tolerant if it possesses two features: (1) symmetric source/drain (S/D) doping profiles and (2) a T-shaped gate. In addition, a relatively positive S/D junction depth with respect to the recessed channel provides a process window for channel depth. Therefore, a new device structure is proposed for the recessed-channel MOSFET, T-gate recessed-channel MOSFET, which can be fabricated with standard Si CMOS processes.

Original languageEnglish (US)
Pages (from-to)1805-1808
Number of pages4
JournalSolid-State Electronics
Volume45
Issue number10
DOIs
StatePublished - Oct 2001
Externally publishedYes

Fingerprint

CMOS
field effect transistors
Doping (additives)
misalignment
profiles
simulation

Keywords

  • CMOSFETs
  • MOSFETs
  • Semiconductor device modeling
  • Silicon

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics

Cite this

On the structure of the recessed-channel MOSFET for sub-100 nm Si CMOS. / Tao, Meng; Varahramyan, Kody.

In: Solid-State Electronics, Vol. 45, No. 10, 10.2001, p. 1805-1808.

Research output: Contribution to journalArticle

Tao, Meng ; Varahramyan, Kody. / On the structure of the recessed-channel MOSFET for sub-100 nm Si CMOS. In: Solid-State Electronics. 2001 ; Vol. 45, No. 10. pp. 1805-1808.
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