On the decreasing significance of large standard cells in technology mapping

Jae Sun Seo, Igor L. Markov, Dennis Sylvester, David Blaauw

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

Technology scaling reduces gate delays while wire delays may increase. Our work studies the interaction of this phenomenon with technology mapping and its impact on modern EDA flows. In particular, we demonstrate that the use of larger standard cells increases the number of long wires and may undermine circuit delay optimization at 65nm and below. Experiments with 130nm, 90nm, 65nm, and 45nm industrial CMOS technology suggest that limiting the use of larger standard cells in technology mapping becomes more effective at 65nm and 45nm node, resulting in up to 12% improvement in critical path delay on large benchmark circuits.

Original languageEnglish (US)
Title of host publication2008 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers, ICCAD 2008
Pages116-121
Number of pages6
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 International Conference on Computer-Aided Design, ICCAD - San Jose, CA, United States
Duration: Nov 10 2008Nov 13 2008

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Other

Other2008 International Conference on Computer-Aided Design, ICCAD
Country/TerritoryUnited States
CitySan Jose, CA
Period11/10/0811/13/08

ASJC Scopus subject areas

  • Software
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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