Abstract
Traditional power optimization and estimation techniques for digital CMOS circuits have focused on the dynamic power dissipation, caused by charging and discharging the load capacitances at the gate outputs. However, as the device size and threshold voltage continue to decrease, the short circuit power dissipation is no longer a negligible factor. We show that previously published models for the short circuit power can not provide the accuracies required for current technologies. To improve the accuracy, we propose a new semi-empirical short circuit power model. Comparison of the proposed model with HSPICE simulation results on CMOS inverters using the Rockwell 0.25 μm CMOS process parameters show that proposed model is significantly more accurate for estimating the short circuit power than the models reported in the literature.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors |
Place of Publication | Piscataway, NJ, United States |
Publisher | IEEE |
Pages | 70-75 |
Number of pages | 6 |
State | Published - 1998 |
Event | Proceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA Duration: Oct 5 1998 → Oct 7 1998 |
Other
Other | Proceedings of the 1998 IEEE International Conference on Computer Design |
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City | Austin, TX, USA |
Period | 10/5/98 → 10/7/98 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering