On short circuit power estimation of CMOS inverters

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

Traditional power optimization and estimation techniques for digital CMOS circuits have focused on the dynamic power dissipation, caused by charging and discharging the load capacitances at the gate outputs. However, as the device size and threshold voltage continue to decrease, the short circuit power dissipation is no longer a negligible factor. We show that previously published models for the short circuit power can not provide the accuracies required for current technologies. To improve the accuracy, we propose a new semi-empirical short circuit power model. Comparison of the proposed model with HSPICE simulation results on CMOS inverters using the Rockwell 0.25 μm CMOS process parameters show that proposed model is significantly more accurate for estimating the short circuit power than the models reported in the literature.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Place of PublicationPiscataway, NJ, United States
PublisherIEEE
Pages70-75
Number of pages6
StatePublished - 1998
Externally publishedYes
EventProceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA
Duration: Oct 5 1998Oct 7 1998

Other

OtherProceedings of the 1998 IEEE International Conference on Computer Design
CityAustin, TX, USA
Period10/5/9810/7/98

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Wang, Q., & Vrudhula, S. B. K. (1998). On short circuit power estimation of CMOS inverters. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (pp. 70-75). IEEE.