Abstract

Unsupervised learning with sparse coding is widely adopted in applications of feature extraction, pattern classification, and compressive sensing. However, even with the state-of-the-art hardware platform of CPUs/GPUs, solving a sparse coding problem is still expensive in computation. In this paper, the resistive cross-point array architecture (CPA) is proposed to achieve on-chip acceleration of sparse coding, especially the matrix/vector operations that are intensively used in the algorithm. Learning and recognition experiments are conducted with the MNIST handwriting dataset. By co-optimizing the algorithm, architecture, circuit, and resistive synaptic devices, SPICE simulation at 65nm demonstrates that the CPA is able to accelerate sparse coding computation by more than 3800X, compared to software running on an 8-core CPU. Furthermore, this work investigates the technological limitations of a realistic resistive CPA, including reduced ON/OFF range of synaptic devices, nonlinearity in programming, spatial and temporal variations, and interconnect parasitics. The results illustrate both enormous opportunities and practical barriers of resistive CPA in real-time learning on a chip.

Original languageEnglish (US)
Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
PublisherAssociation for Computing Machinery
Pages195-197
Number of pages3
Volume20-22-May-2015
ISBN (Print)9781450334747
DOIs
StatePublished - May 20 2015
Event25th Great Lakes Symposium on VLSI, GLSVLSI 2015 - Pittsburgh, United States
Duration: May 20 2015May 22 2015

Other

Other25th Great Lakes Symposium on VLSI, GLSVLSI 2015
CountryUnited States
CityPittsburgh
Period5/20/155/22/15

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'On-chip sparse learning with resistive cross-point array architecture'. Together they form a unique fingerprint.

  • Cite this

    Yu, S., & Cao, Y. (2015). On-chip sparse learning with resistive cross-point array architecture. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (Vol. 20-22-May-2015, pp. 195-197). Association for Computing Machinery. https://doi.org/10.1145/2742060.2743757