On-chip interconnect modeling technologies

Enis Dengi, Ronald A. Rohrer

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

On-chip interconnect must be accounted for at all levels of the design hierarchy, starting with synthesis, through physical design and ending with verification. Developing a compact model for an interconnect is important to render consistent interconnect models at different levels of the design hierarchy and achieve design convergence. This development requires on-chip modeling technologies for post-layout verification, called `parasitic extraction', and characterization/silicon-correlation which is important to interconnect modeling at all levels.

Original languageEnglish (US)
Number of pages1
StatePublished - Dec 1 1997
Externally publishedYes
EventProceedings of the 1997 6th Topical Meeting on Electrical Performance of Electronic Packaging - San Jose, CA, USA
Duration: Oct 27 1997Oct 29 1997

Other

OtherProceedings of the 1997 6th Topical Meeting on Electrical Performance of Electronic Packaging
CitySan Jose, CA, USA
Period10/27/9710/29/97

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ASJC Scopus subject areas

  • Engineering(all)

Cite this

Dengi, E., & Rohrer, R. A. (1997). On-chip interconnect modeling technologies. Paper presented at Proceedings of the 1997 6th Topical Meeting on Electrical Performance of Electronic Packaging, San Jose, CA, USA, .

On-chip interconnect modeling technologies. / Dengi, Enis; Rohrer, Ronald A.

1997. Paper presented at Proceedings of the 1997 6th Topical Meeting on Electrical Performance of Electronic Packaging, San Jose, CA, USA, .

Research output: Contribution to conferencePaper

Dengi, E & Rohrer, RA 1997, 'On-chip interconnect modeling technologies' Paper presented at Proceedings of the 1997 6th Topical Meeting on Electrical Performance of Electronic Packaging, San Jose, CA, USA, 10/27/97 - 10/29/97, .
Dengi E, Rohrer RA. On-chip interconnect modeling technologies. 1997. Paper presented at Proceedings of the 1997 6th Topical Meeting on Electrical Performance of Electronic Packaging, San Jose, CA, USA, .
Dengi, Enis ; Rohrer, Ronald A. / On-chip interconnect modeling technologies. Paper presented at Proceedings of the 1997 6th Topical Meeting on Electrical Performance of Electronic Packaging, San Jose, CA, USA, .1 p.
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