Abstract
This paper presents two novel sorting network-based architectures for computing high sample rate non recursive rank order filters. The proposed architectures consist of significantly fewer comparators than existing architectures that are based on bubble-sort and Batcher's odd-even merge sort. The reduction in the number of comparators is obtained by sorting the columns of the window only once, and by merging the sorted columns in a way such that the set of candidate elements for the output is very small. The number of comparators per output are reduced even further by processing a block of outputs at a time.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Publisher | IEEE |
| Pages | 89-92 |
| Number of pages | 4 |
| Volume | 3 |
| State | Published - 1994 |
| Event | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England Duration: May 30 1994 → Jun 2 1994 |
Other
| Other | Proceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) |
|---|---|
| City | London, England |
| Period | 5/30/94 → 6/2/94 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials