For sub-65nm technology nodes, Negative Bias Temperature Instability (NBTI) has become a primary limiting factor of circuit lifetime. During the past few years, researchers have spent considerable and continuous efforts on modeling and characterization of NBTI-caused delay degradation at different design levels. Searching for solutions which can effectively reduce NBTI impact on circuit delay is still under way. In this work, we use node criticality computation to drive NBTI aware timing analysis and optimization. Circuits after being applied this optimization flow show strong resistance to NBTI delay degradation. Particularly, for the first time, we propose node criticality computation algorithm under the NBTI aware timing analysis and optimization framework and give answers to the following questions which have not been answered yet. They are: (1) how to define node criticality in a circuit under NBTI effect; (2) how to find the critical nodes which once are protected NBTI timing degradation will be effectively reduced. Experimental results show that by protecting the critical nodes found by this framework, circuit delay degradation can be reduced by up to 50%.