Node criticality computation for circuit timing analysis and optimization under NBTI effect

Wenping Wang, Shengqi Yang, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

For sub-65nm technology nodes, Negative Bias Temperature Instability (NBTI) has become a primary limiting factor of circuit lifetime. During the past few years, researchers have spent considerable and continuous efforts on modeling and characterization of NBTI-caused delay degradation at different design levels. Searching for solutions which can effectively reduce NBTI impact on circuit delay is still under way. In this work, we use node criticality computation to drive NBTI aware timing analysis and optimization. Circuits after being applied this optimization flow show strong resistance to NBTI delay degradation. Particularly, for the first time, we propose node criticality computation algorithm under the NBTI aware timing analysis and optimization framework and give answers to the following questions which have not been answered yet. They are: (1) how to define node criticality in a circuit under NBTI effect; (2) how to find the critical nodes which once are protected NBTI timing degradation will be effectively reduced. Experimental results show that by protecting the critical nodes found by this framework, circuit delay degradation can be reduced by up to 50%.

Original languageEnglish (US)
Title of host publicationProceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008
Pages763-768
Number of pages6
DOIs
StatePublished - 2008
Event9th International Symposium on Quality Electronic Design, ISQED 2008 - San Jose, CA, United States
Duration: Mar 17 2008Mar 19 2008

Other

Other9th International Symposium on Quality Electronic Design, ISQED 2008
CountryUnited States
CitySan Jose, CA
Period3/17/083/19/08

Fingerprint

Timing circuits
Delay circuits
Degradation
Networks (circuits)
Negative bias temperature instability

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Wang, W., Yang, S., & Cao, Y. (2008). Node criticality computation for circuit timing analysis and optimization under NBTI effect. In Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008 (pp. 763-768). [4479834] https://doi.org/10.1109/ISQED.2008.4479834

Node criticality computation for circuit timing analysis and optimization under NBTI effect. / Wang, Wenping; Yang, Shengqi; Cao, Yu.

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008. 2008. p. 763-768 4479834.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wang, W, Yang, S & Cao, Y 2008, Node criticality computation for circuit timing analysis and optimization under NBTI effect. in Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008., 4479834, pp. 763-768, 9th International Symposium on Quality Electronic Design, ISQED 2008, San Jose, CA, United States, 3/17/08. https://doi.org/10.1109/ISQED.2008.4479834
Wang W, Yang S, Cao Y. Node criticality computation for circuit timing analysis and optimization under NBTI effect. In Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008. 2008. p. 763-768. 4479834 https://doi.org/10.1109/ISQED.2008.4479834
Wang, Wenping ; Yang, Shengqi ; Cao, Yu. / Node criticality computation for circuit timing analysis and optimization under NBTI effect. Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008. 2008. pp. 763-768
@inproceedings{e89d826961654d21be73661a817ce82c,
title = "Node criticality computation for circuit timing analysis and optimization under NBTI effect",
abstract = "For sub-65nm technology nodes, Negative Bias Temperature Instability (NBTI) has become a primary limiting factor of circuit lifetime. During the past few years, researchers have spent considerable and continuous efforts on modeling and characterization of NBTI-caused delay degradation at different design levels. Searching for solutions which can effectively reduce NBTI impact on circuit delay is still under way. In this work, we use node criticality computation to drive NBTI aware timing analysis and optimization. Circuits after being applied this optimization flow show strong resistance to NBTI delay degradation. Particularly, for the first time, we propose node criticality computation algorithm under the NBTI aware timing analysis and optimization framework and give answers to the following questions which have not been answered yet. They are: (1) how to define node criticality in a circuit under NBTI effect; (2) how to find the critical nodes which once are protected NBTI timing degradation will be effectively reduced. Experimental results show that by protecting the critical nodes found by this framework, circuit delay degradation can be reduced by up to 50{\%}.",
author = "Wenping Wang and Shengqi Yang and Yu Cao",
year = "2008",
doi = "10.1109/ISQED.2008.4479834",
language = "English (US)",
isbn = "0769531172",
pages = "763--768",
booktitle = "Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008",

}

TY - GEN

T1 - Node criticality computation for circuit timing analysis and optimization under NBTI effect

AU - Wang, Wenping

AU - Yang, Shengqi

AU - Cao, Yu

PY - 2008

Y1 - 2008

N2 - For sub-65nm technology nodes, Negative Bias Temperature Instability (NBTI) has become a primary limiting factor of circuit lifetime. During the past few years, researchers have spent considerable and continuous efforts on modeling and characterization of NBTI-caused delay degradation at different design levels. Searching for solutions which can effectively reduce NBTI impact on circuit delay is still under way. In this work, we use node criticality computation to drive NBTI aware timing analysis and optimization. Circuits after being applied this optimization flow show strong resistance to NBTI delay degradation. Particularly, for the first time, we propose node criticality computation algorithm under the NBTI aware timing analysis and optimization framework and give answers to the following questions which have not been answered yet. They are: (1) how to define node criticality in a circuit under NBTI effect; (2) how to find the critical nodes which once are protected NBTI timing degradation will be effectively reduced. Experimental results show that by protecting the critical nodes found by this framework, circuit delay degradation can be reduced by up to 50%.

AB - For sub-65nm technology nodes, Negative Bias Temperature Instability (NBTI) has become a primary limiting factor of circuit lifetime. During the past few years, researchers have spent considerable and continuous efforts on modeling and characterization of NBTI-caused delay degradation at different design levels. Searching for solutions which can effectively reduce NBTI impact on circuit delay is still under way. In this work, we use node criticality computation to drive NBTI aware timing analysis and optimization. Circuits after being applied this optimization flow show strong resistance to NBTI delay degradation. Particularly, for the first time, we propose node criticality computation algorithm under the NBTI aware timing analysis and optimization framework and give answers to the following questions which have not been answered yet. They are: (1) how to define node criticality in a circuit under NBTI effect; (2) how to find the critical nodes which once are protected NBTI timing degradation will be effectively reduced. Experimental results show that by protecting the critical nodes found by this framework, circuit delay degradation can be reduced by up to 50%.

UR - http://www.scopus.com/inward/record.url?scp=49749135199&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=49749135199&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2008.4479834

DO - 10.1109/ISQED.2008.4479834

M3 - Conference contribution

AN - SCOPUS:49749135199

SN - 0769531172

SN - 9780769531175

SP - 763

EP - 768

BT - Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

ER -