New Viterbi decoder design for code rate k/n

Hsiang ling Li, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel VLSI architecture is proposed for implementing a long constraint length Viterbi Decoder (VD) for code rate k/n. This architecture is based on the encoding structure where k input bits are shifted into k shift registers in each cycle. The architecture is designed in a hierarchical manner by breaking the system into several levels and designing each level independently. At each level, the number of computation units, the interconnection between the units as well as allocation and scheduling issues have been determined. In-place storage of accumulated path metrics and trace back implementation of the survivor memory have also been addressed. The resulting architecture is regular, flexible and achieves a better than linear tradeoff between hardware complexity and computation time.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Editors Anon
PublisherIEEE
Pages549-552
Number of pages4
Volume1
StatePublished - 1995
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: Apr 30 1995May 3 1995

Other

OtherProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3)
CitySeattle, WA, USA
Period4/30/955/3/95

Fingerprint

Shift registers
Scheduling
Hardware
Data storage equipment

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Li, H. L., & Chakrabarti, C. (1995). New Viterbi decoder design for code rate k/n. In Anon (Ed.), Proceedings - IEEE International Symposium on Circuits and Systems (Vol. 1, pp. 549-552). IEEE.

New Viterbi decoder design for code rate k/n. / Li, Hsiang ling; Chakrabarti, Chaitali.

Proceedings - IEEE International Symposium on Circuits and Systems. ed. / Anon. Vol. 1 IEEE, 1995. p. 549-552.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Li, HL & Chakrabarti, C 1995, New Viterbi decoder design for code rate k/n. in Anon (ed.), Proceedings - IEEE International Symposium on Circuits and Systems. vol. 1, IEEE, pp. 549-552, Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3), Seattle, WA, USA, 4/30/95.
Li HL, Chakrabarti C. New Viterbi decoder design for code rate k/n. In Anon, editor, Proceedings - IEEE International Symposium on Circuits and Systems. Vol. 1. IEEE. 1995. p. 549-552
Li, Hsiang ling ; Chakrabarti, Chaitali. / New Viterbi decoder design for code rate k/n. Proceedings - IEEE International Symposium on Circuits and Systems. editor / Anon. Vol. 1 IEEE, 1995. pp. 549-552
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