New viterbi decoder design for code rate K/N

Hsiang ling Li, Chaitali Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A novel VLSI architecture is proposed for implementing a long constraint length Viterbi Decoder (VD) for code rate k/n. This architecture is based on the encoding structure where k input bits are shifted into k shift registers in each cycle. The architecture is designed in a hierarchical manner by breaking the system into several levels and designing each level independently. At each level, the number of computation units, the interconnection between the units as well as allocation and scheduling issues have been determined. In-place storage of accumulated path metrics and trace back implementation of the survivor memory have also been addressed. The resulting architecture is regular, flexible and achieves a better than linear tradeoff between hardware complexity and computation time.

Original languageEnglish (US)
Title of host publicationICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Pages2743-2746
Number of pages4
Volume4
StatePublished - 1995
EventProceedings of the 1995 20th International Conference on Acoustics, Speech, and Signal Processing. Part 2 (of 5) - Detroit, MI, USA
Duration: May 9 1995May 12 1995

Other

OtherProceedings of the 1995 20th International Conference on Acoustics, Speech, and Signal Processing. Part 2 (of 5)
CityDetroit, MI, USA
Period5/9/955/12/95

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Acoustics and Ultrasonics

Cite this

Li, H. L., & Chakrabarti, C. (1995). New viterbi decoder design for code rate K/N. In ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings (Vol. 4, pp. 2743-2746)