TY - JOUR
T1 - New generation of predictive technology model for sub-45 nm early design exploration
AU - Zhao, Wei
AU - Cao, Yu
N1 - Funding Information:
Manuscript received May 3, 2006; revised August 15, 2006. This work was supported in part by the MARCO Focus Center for Circuit and System Solution and in part by the Materials, Structures, and Devices Focus Center. The review of this paper was arranged by Editor M. J. Deen. The authors are with the Department of Electrical Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: wei.zhao@asu.edu). Color version of Figs. 3–8 are available at http://www.ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2006.884077
PY - 2006/11
Y1 - 2006/11
N2 - A predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and correlations among model parameters, must be included. In this paper, a new generation of predictive technology model (PTM) is developed to accomplish this goal. Based on physical models and early-stage silicon data, the PTM of bulk CMOS is successfully generated for 130- to 32-nm technology nodes, with an Leff of as low as 13 nm. The accuracy of PTM predictions is comprehensively verified: The error of Ion is below 10% for both n-channel MOS and p-channel MOS. By tuning only ten primary parameters, the PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime, particularly the interactions among Leff, Vth, mobility, and saturation velocity. A website has been established for the release of PTM: http://www.eas.asu.edu/~ptm.
AB - A predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and correlations among model parameters, must be included. In this paper, a new generation of predictive technology model (PTM) is developed to accomplish this goal. Based on physical models and early-stage silicon data, the PTM of bulk CMOS is successfully generated for 130- to 32-nm technology nodes, with an Leff of as low as 13 nm. The accuracy of PTM predictions is comprehensively verified: The error of Ion is below 10% for both n-channel MOS and p-channel MOS. By tuning only ten primary parameters, the PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime, particularly the interactions among Leff, Vth, mobility, and saturation velocity. A website has been established for the release of PTM: http://www.eas.asu.edu/~ptm.
KW - Mobility degradation
KW - Predictive modeling
KW - Process variation
KW - Saturation velocity
KW - Threshold voltage
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U2 - 10.1109/TED.2006.884077
DO - 10.1109/TED.2006.884077
M3 - Article
AN - SCOPUS:33750600861
SN - 0018-9383
VL - 53
SP - 2816
EP - 2823
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 11
ER -