NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures

Pai Yu Chen; Xiaochen Peng; Shimeng Yu

doi:10.1109/IEDM.2017.8268337

NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures

Pai Yu Chen, Xiaochen Peng, Shimeng Yu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

140 Scopus citations

Abstract

Neuro Sim+ is an integrated simulation framework for benchmarking synaptic devices and array architectures in terms of the system-level learning accuracy and hardware performance metrics. It has a hierarchical organization from the device level (transistor technology and memory cell models) to the circuit level (synaptic array architectures and neuron periphery) and then to the algorithm level (neural network topologies). In this work, we study the impact of the "analog" eNVM non-ideal device properties and benchmark the trade-offs of SRAM, digital and analog eNVM based array architectures for online learning and offline classification. The source code of NeuroSim+ version 1.0 is publicly available at https://github.com/neurosim/MLP-NeuroSim.

Original language	English (US)
Title of host publication	2017 IEEE International Electron Devices Meeting, IEDM 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	6.1.1-6.1.4
ISBN (Electronic)	9781538635599
DOIs	https://doi.org/10.1109/IEDM.2017.8268337
State	Published - Jan 23 2018
Event	63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States Duration: Dec 2 2017 → Dec 6 2017

Other

Other	63rd IEEE International Electron Devices Meeting, IEDM 2017
Country/Territory	United States
City	San Francisco
Period	12/2/17 → 12/6/17

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/IEDM.2017.8268337

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NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures. / Chen, Pai Yu; Peng, Xiaochen; Yu, Shimeng.
2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 6.1.1-6.1.4.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chen, PY, Peng, X & Yu, S 2018, NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures. in 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., pp. 6.1.1-6.1.4, 63rd IEEE International Electron Devices Meeting, IEDM 2017, San Francisco, United States, 12/2/17. https://doi.org/10.1109/IEDM.2017.8268337

@inproceedings{051f0aefbad548d3a4ffb62a830e7487,

title = "NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures",

abstract = "Neuro Sim+ is an integrated simulation framework for benchmarking synaptic devices and array architectures in terms of the system-level learning accuracy and hardware performance metrics. It has a hierarchical organization from the device level (transistor technology and memory cell models) to the circuit level (synaptic array architectures and neuron periphery) and then to the algorithm level (neural network topologies). In this work, we study the impact of the {"}analog{"} eNVM non-ideal device properties and benchmark the trade-offs of SRAM, digital and analog eNVM based array architectures for online learning and offline classification. The source code of NeuroSim+ version 1.0 is publicly available at https://github.com/neurosim/MLP-NeuroSim.",

author = "Chen, {Pai Yu} and Xiaochen Peng and Shimeng Yu",

year = "2018",

month = jan,

day = "23",

doi = "10.1109/IEDM.2017.8268337",

language = "English (US)",

pages = "6.1.1--6.1.4",

booktitle = "2017 IEEE International Electron Devices Meeting, IEDM 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "63rd IEEE International Electron Devices Meeting, IEDM 2017 ; Conference date: 02-12-2017 Through 06-12-2017",

}

TY - GEN

T1 - NeuroSim+

T2 - 63rd IEEE International Electron Devices Meeting, IEDM 2017

AU - Chen, Pai Yu

AU - Peng, Xiaochen

AU - Yu, Shimeng

PY - 2018/1/23

Y1 - 2018/1/23

N2 - Neuro Sim+ is an integrated simulation framework for benchmarking synaptic devices and array architectures in terms of the system-level learning accuracy and hardware performance metrics. It has a hierarchical organization from the device level (transistor technology and memory cell models) to the circuit level (synaptic array architectures and neuron periphery) and then to the algorithm level (neural network topologies). In this work, we study the impact of the "analog" eNVM non-ideal device properties and benchmark the trade-offs of SRAM, digital and analog eNVM based array architectures for online learning and offline classification. The source code of NeuroSim+ version 1.0 is publicly available at https://github.com/neurosim/MLP-NeuroSim.

AB - Neuro Sim+ is an integrated simulation framework for benchmarking synaptic devices and array architectures in terms of the system-level learning accuracy and hardware performance metrics. It has a hierarchical organization from the device level (transistor technology and memory cell models) to the circuit level (synaptic array architectures and neuron periphery) and then to the algorithm level (neural network topologies). In this work, we study the impact of the "analog" eNVM non-ideal device properties and benchmark the trade-offs of SRAM, digital and analog eNVM based array architectures for online learning and offline classification. The source code of NeuroSim+ version 1.0 is publicly available at https://github.com/neurosim/MLP-NeuroSim.

UR - http://www.scopus.com/inward/record.url?scp=85045198156&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85045198156&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2017.8268337

DO - 10.1109/IEDM.2017.8268337

M3 - Conference contribution

AN - SCOPUS:85045198156

SP - 6.1.1-6.1.4

BT - 2017 IEEE International Electron Devices Meeting, IEDM 2017

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 2 December 2017 through 6 December 2017

ER -

NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures

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