Neuromorphic hardware accelerator for SNN inference based on STT-RAM crossbar arrays

Shruti R. Kulkarni, Deepak Vinayak Kadetotad, Shihui Yin, Jae Sun Seo, Bipin Rajendran

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

In this paper, we propose a Spin Transfer Torque RAM (STT-RAM) based neurosynaptic core to implement a hardware accelerator for Spiking Neural Networks (SNNs), which mimic the time-based signal encoding and processing mechanisms of the human brain. The computational core consists of a crossbar array of non-volatile STT-RAMs, read/write peripheral circuits, and digital logic for the spiking neurons. Inter-core communication is realized through on-chip routing network by sending/receiving spike packets. Unlike prior works that use multi-level states of non-volatile memory (NVM) devices for the synaptic weights, we use the technologically-mature STT-RAM devices for binary data storage. The design studies are conducted using a compact model for STT-RAM devices, tuned to capture the state-of-the-art experimental results. Our design avoids the need for expensive ADCs and DACs, enabling instantiation of large NVM arrays for our core. We show that the STT-RAM based neurosynaptic core designed in 28 nm technology node has approximately 6× higher throughput per unit Watt and unit area than an equivalent SRAM based design. Our design also achieves ∼ 2× higher performance per Watt compared to other memristive neural network accelerator designs in the literature.

Original languageEnglish (US)
Title of host publication2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages438-441
Number of pages4
ISBN (Electronic)9781728109961
DOIs
StatePublished - Nov 2019
Event26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 - Genoa, Italy
Duration: Nov 27 2019Nov 29 2019

Publication series

Name2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019

Conference

Conference26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019
CountryItaly
CityGenoa
Period11/27/1911/29/19

Keywords

  • Crossbar arrays
  • Neuromorphic hardware
  • Non-volatile memories
  • Spiking neural networks
  • STT-RAM

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Control and Optimization
  • Computer Networks and Communications
  • Hardware and Architecture

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  • Cite this

    Kulkarni, S. R., Kadetotad, D. V., Yin, S., Seo, J. S., & Rajendran, B. (2019). Neuromorphic hardware accelerator for SNN inference based on STT-RAM crossbar arrays. In 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019 (pp. 438-441). [8964886] (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS46596.2019.8964886