Neural processing of semantic networks

Summary form only given, as follows. A dynamically reconfigurable architecture for parallel processing of semantic networks is described. The proposed architecture is made up of a network of Boolean McCulloch-Pitts neuron-like cells, each dedicated to one vertex of a semantic network and its associated edges. By partitioning each cell and integrating the neural-like network into several functional blocks, a highly regularly structured reconfigurable processing unit is achievable. Such a processing unit is capable of storing symbolic assertions and performing parallel search and deduction within its collection of knowledge. Potentially this architecture can be realized by the VLSI technology, and the design approach also exploits an application for on-chip expert systems.