Near-planar monolithic integration of GaAs FETs and LEDs with use of a thermal oxide isolation (TOI) layer

C. B. Wheeler, S. Daryanani, Yong-Hang Zhang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new integration method that relies on the thermal oxidation of AlAs to form a buried current confining and isolation layer for light emitting device (LED) and field effect transistors (FET) is presented. The buried oxide layer is situated under the FET channel such that the transistor is effectively stacked on top of the LED (or VCSEL). The oxide layer is also used to form a current injection aperture in the LED and directs current flow vertically through this device. With this proposed method, there is the possibility of integrating GaAs FETs and vertical cavity surface emitting lasers (VCELs) photodetectors on the same chip.

Original languageEnglish (US)
Title of host publicationConference Proceedings - Lasers and Electro-Optics Society Annual Meeting-LEOS
Editors Anon
PublisherIEEE
Pages259-260
Number of pages2
Volume11
StatePublished - 1997
EventProceedings of the 1997 Conference on Lasers and Electro-Optics, CLEO - Baltimore, MD, USA
Duration: May 18 1997May 23 1997

Other

OtherProceedings of the 1997 Conference on Lasers and Electro-Optics, CLEO
CityBaltimore, MD, USA
Period5/18/975/23/97

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering

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  • Cite this

    Wheeler, C. B., Daryanani, S., & Zhang, Y-H. (1997). Near-planar monolithic integration of GaAs FETs and LEDs with use of a thermal oxide isolation (TOI) layer. In Anon (Ed.), Conference Proceedings - Lasers and Electro-Optics Society Annual Meeting-LEOS (Vol. 11, pp. 259-260). IEEE.